Node-Red implementation of HDL BusPro (SmartBus) protocol http://hdlautomation.com

8-bit ALU in Verilog.

Let's write RISC-V CPU in Veryl!

Two Sobel filters designed in VHDL and HLS with Vivado Tools and implemented in ZYBO SoC

FPGA LCD MIPI or DPI

Project file made on Quartus in Verilog. With components: Ripple Carry, Full Adder and Half Adder

The VHDL93 Docset provides offline access to VHDL-93 documentation for users of Zeal and Dash. This docset includes syntax references, examples, and explanations of key VHDL concepts.

HDL for Node-RED, utilizing pure JavaScript HDL Buspro driver

A final project for FPGA_SOC course

A universal language of signs for designing and proving purely mechanical computers, inspired by Charles Babbage's original notation.

HDL, Linux and other guidelines, applications, articles

An International Obfuscated *HDL Code Contest (Why Verilog? For the name to be good: IOVCC)

Functional assays development for HDL and Plasma: Data analyses, visuals, reports

FPGA-TFT-MIPI-or-DPI

Project for Logic Design 2 course taken during Spring 2022 semester. We implemented the Advanced encryption standard (AES128, AES192, AES256) in this project using Verilog and used a wrapper module on the DE1-SOC kit to test it.

ALUminium is a CPLD/FPGA code for a 8bits arithmetic–logic unit, made for processor like GP8B

Sharif University of Technology - Spring 2019 - Digital System Design Course Project

custom lambda-function like circuits for FPGA is the future

An exploration of a circuit description language for general circuits using rust. In particular PCB's.