Verilog Implementation of an ARM LEGv8 CPU

FPGA Sound Blaster over LPC bus experiments

Design of a Processor Microarchitecture Supporting a Chosen Subset of RISC-V ISA Instructions.

A custom processor implemented in Verilog HDL for image down sampling for UOM's EN3030 Circuits and Systems Design module ❄

Reduced MIPS 32-bit Processor

A 16-bit, 5-stage RISC processor. RTL description in Verilog. Includes assembler, simulator, and example programs.

16-bit PC based on SediCiPUv2 CPU

Computer Architecture-MIPS Processor simulation in verilog with self developed ISA

A 16-bit Instruction Set Architecture.

A custom RISC 16-bit CPU running at 50MHz on an FPGA

Modular 16-bit RISC processor (Hack ISA) implemented in Verilog HDL, featuring single-cycle execution and Harvard architecture.

A 32-bit MIPS ISA single-cycle processor design, implemented in Verilog.