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ip-xact
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Translates IPXACT XML to synthesizable VHDL or SystemVerilog
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Jan 28, 2026 - Python
Import and export IP-XACT XML register models
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Nov 5, 2025 - Python
RTL/hardware fork of graphify. Upstream's SystemVerilog extractor produced no edges; this fixes it (modules, instances, packages, includes, interfaces, binds) and adds Make, Tcl, IP-XACT, SymbiYosys and Verilator-testbench extractors — turning an HDL IP catalog into a queryable knowledge graph.
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Jun 9, 2026 - Python
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