nvc

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PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities

c verification verilog virtual vivado modelling icarus-verilog ghdl cosim pcie pli bfm verilator nvc xsim questa-sim

🛸 Optimized Video Native Interface - The fastest video editing GPU-accelerated pipeline.

video ffmpeg cuda nvidia moviepy nvenc nvdec nvc

Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.

vhdl gdb modelsim questasim ghdl openocd jtag nvc fli cosimulation vhpi

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