A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM, 8-bit AVR and 32-bit RISC-V architectures.

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

Functional verification project for the CORE-V family of RISC-V cores.

RISC-V Zve32x Vector Coprocessor

Assembly Guide

A RISC-V emulator for the 8051 (MCS-51) microcontroller.

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code

Simple Yet Powerful RISC-V Computer

Chisel RISC-V Vector 1.0 Implementation

32-bit RISC-V Forth for microcontrollers

CPU assembly examples

Fast constant-time AES implementations on 32-bit architectures

Bare-metal Forth implementation for RISC-V

Tiny RISC-V machine code monitor written in RISC-V assembly.

A collection of useful mips templates

A little risc-v assembly OS that can run DOOM on a QEMU riscv64 Virt

high performance AES implementations optimized for cortex-m microcontrollers

Materials for the "Computer Architecture and Operating Systems" course taught at Faculty of Computer Science of Higher School of Economics

A baremetal experiment of Allwinner D1, without FEL