Open-source parametrizeable cache sub‑system generator in Chisel lang for RISC‑V systems

This is my master's degree final thesis. I'll be adding pipelining capabilities to an existing RISC-V single cycle design

Aleph is a single cycle processor that carries out one instruction in a single clock cycle

chiselでCPUを自作するぞリポジトリ

A basic implemention of 8 lane vector SIMD in RISC-V 5 Stage Pipeline, written in Chisel and Scala.

A single-cycle RV64i RISC-V Processor

Refactoring Ibex with Chisel

A simple RISC-V project for a University course on computer architecture

Implementation of RISC-V Pipeline

Make writing trivial inst{ruction,rumentation}s for RocketChip as simple as writing the C code

A small framework to simplify the creation of custom instruction for the VexRiscv.

Source files for SiFive's Freedom platforms (port to Zeowaa board with Cyclone 4 chip: see intel-zeowaa branch)

This is my graduation project, a simple processor soft core, which implements RV32I ISA.

An unpipelined 32-bit RISC-V CPU, written in Chisel.

RISC-V emulator writen in Scala

A RISC-V vector processor written in Chisel HDL.