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soft-core

Here are 9 public repositories matching this topic...

matt-alencar / fpga-uart-tx-rx

Basic UART TX/RX module for FPGA

fpga verilog uart hdl uart-protocol soft-core uart-interface

Updated Oct 18, 2018
Verilog

semahawk / icarium

Trying to implement a soft core SoC

verilog verilog-hdl wishbone soft-core system-on-chip softcore wishbone-bus

Updated Apr 6, 2019
Verilog

SaraBaradaran / MIPS-Processor

Implementation of MIPS Processor Modules Using Verilog

mips-assembly verilog soft-core hardware-implementation proccessor

Updated May 11, 2021
Verilog

WangXuan95 / FPGA-DDR-SDRAM

An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

fpga controller rtl verilog soft-core axi4 ddr-sdram ddr1

Updated Sep 15, 2023
Verilog

AndrejChoo / AVR_like_core_on_verilog

Soft core with support for the AVR8 instructions on verilog

avr verilog soft-core

Updated Oct 3, 2023
Verilog

ArbnorSh / RV-PipelineCore

RISC-V processor in compliance with RV32IMZicsr

cpu processor vhdl soc ghdl risc-v soft-core verilator

Updated Sep 15, 2024
Verilog

alinja / alpus_riscv_cpu

A study of soft-core CPUs for use with FPGA designs

fpga vhdl gcc riscv soc risc-v baremetal soft-core system-on-chip soft-cpu

Updated Dec 6, 2024
Verilog

ZipCPU / zipcpu

A small, light weight, RISC CPU soft core

cpu fpga verilog cross-compiler wishbone soft-core verilator zipcpu wishbone-bus risc-cpu

Updated Aug 9, 2025
Verilog

RISC-KC / basic_rv32s

🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.

Updated Oct 12, 2025
Verilog

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