VHDL 2008/93/87 simulator

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…

An implementation of DisplayPort protocol for FPGAs

Second version of homemade 30 MHz - 6 GHz VNA

Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA

WIP Graphics layer and inter IC communication for the Spartan Edge Accelerator fpga/mcu hybrid board

FPGA LVDS LCD driver