PicoRV32 - A Size-Optimized RISC-V CPU

Verilog Ethernet components for FPGA implementation

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Open source FPGA-based NIC and platform for in-network compute

RTL, Cmodel, and testbench for NVDLA

Must-have verilog systemverilog modules

Verilog AXI components for FPGA implementation

HDL libraries and projects

The Ultra-Low Power RISC-V Core

The USRP™ Hardware Driver Repository

The RIFFA development repository

A High-performance Timing Analysis Tool for VLSI Systems

mor1kx - an OpenRISC 1000 processor IP core

Example designs showing different ways to use F4PGA toolchains.

A Video display simulator