The FPGA synthesis constraints file includes the waveform parameter, which defines the clock duty cycle. By default, if this parameter is not explicitly specified, the duty cycle is assumed to be (50%) of the clock period.

The waveform parameter is expressed as two values:

$$(t_1; t_2)$$

where (t_1) represents the time of the first transition (typically (0)), and ($t_2$) represents the time of the second transition in nanoseconds. In this case, it is defined for all signals as:

$$(0; 5,\text{ns})$$

Please note that when both clock edges are used, it may be necessary to introduce clock uncertainties to provide adequate setup and hold timing margins.