RISC-V Intergration#3724
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SChernykh
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Good initial work! I guess you just went the path of "fix compile errors" until it compiled and passed tests?
Please, for each of the new files, add the correct credits at the top (either for the original authors, or for yourself if you wrote the code). Ideally, also add the links to where you took the code from - it will make maintaining it much easier.
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Will do. Pretty much, but I also needed to make some additions so that the correct libraries are loaded and that it actually works "properly". Once I confirmed that RANDOMX compiles and runs, I was sure I could figure out some way to get XMRig to compile for RISC-V. I mean, Bitmain made it work somehow with the X5.
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As soon as this PR is merged, I will add the RISC-V JIT compiler from the reference RandomX repository - it shouldn't be that hard now. I can only test it with qemu though, so I would appreciate if you test it once it's added. |
| # RISC-V-specific optimizations for maximum performance | ||
| # Use vector extensions (V) and bit manipulation extensions (Zba, Zbb, Zbc, Zbs) | ||
| set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=rv64gcv_zba_zbb_zbc_zbs") | ||
| set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=rv64gcv_zba_zbb_zbc_zbs") |
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This crashes with Illegal instruction in my qemu. Use this as the reference: https://github.com/tevador/RandomX/blob/master/CMakeLists.txt#L185-L207
It should compile and run with rv64gc only, even if the performance is lower. Of course you can enable additional extensions when compiling on the real CPU (using the try_run function from there).
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One more thing I noticed: it reports CPU as 32-bit because you forgot to fix |
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Addressed the comments
I've recompiled it on the RV2 and run it with no issues. |
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Almost everything is good, you just need to clean up now:
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I have almost finished porting the RISC-V JIT compiler from https://github.com/tevador/RandomX/ so once this PR is merged, I'll make a PR with the JIT compiler and you will be able to test it. |
Done 👍 |
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All good. I will soon open a new PR with everything in it (your changes and my changes) against |
Tested on: Ky X1 8-core RISC-V AI CPU (via ORANGE PI RV2)
I have successfully integrated initial RISC-V support and conducted preliminary testing on an ORANGE PI RV2 board. With initial optimisations, the board achieved 36 H/s. While this performance is modest, it establishes a functional foundation and opens significant opportunities for testing and optimisation on higher-end RISC-V boards and platforms in the future.
I've recompiled on X86 and a Raspberry Pi 3 and 5 to make sure everything is still compatible.
Build System Updates (CMake)
The following changes were made to the CMake build scripts to enable cross-compilation and native compilation for RISC-V:
Architecture Detection: Added RISC-V detection logic within cmake/cpu.cmake, cmake/flags.cmake, and other critical build scripts.
Aggressive Optimisations: Implemented new compiler flags specifically for RISC-V, targeting aggressive optimisation (-march=rv64gcv_zba_zbb_zbc_zbs, loop unrolling, vectorisation, etc.).
Feature Exclusion: Disabled all x86-specific instruction set features (SSE, AVX, VAES, MSR) to ensure successful compilation on RISC-V targets.
Source Code Adaptations
Significant modifications were required across the CPU backend, crypto engine, and memory management layers.
Architecture-Specific Files: Added architecture-specific source files (lscpu_riscv.cpp) and updated existing ones (BasicCpuInfo_arm.cpp) to handle RISC-V architecture details.
Runtime Feature Detection: Implemented custom logic for runtime detection of crypto and vector extensions by parsing /proc/cpuinfo.
Vector Intrinsic Compatibility: Introduced new compatibility layers (sse2rvv.h, sse2rvv_optimized.h, sse2rvv_scalar_backup.h) to map x86 SSE intrinsics to RVV (RISC-V Vector) intrinsics.
RISC-V Crypto Support: Added conditional support for native RISC-V crypto extensions (AES, SHA2, SHA3, bit manipulation) via riscv_crypto.h, including compile-time and runtime detection.
Cleanup: All x86- and ARM-specific code is now conditionally excluded when compiling for RISC-V.
Dataset Initialisation: Added new dataset initialisation logic specifically for RISC-V (RxDataset_riscv.h), featuring adaptive threading and cache-aware memory operations.
Temporary AES Fallback: Forced the use of software AES on RISC-V until native hardware intrinsics are fully stable and integrated.
Vectorised memory and arithmetic operations using RVV when the extension is detected.
Aggressive compiler optimisations, including vector extensions, bit manipulation, loop unrolling, and math optimisations, are enabled by default to achieve maximum hashing performance.
While this helped the board go from 14 H/s to 33 H/s to 36 H/s I am not sure how this will work out on other CPUs