Write Language Servers that comply with 3.17 of the LSP Specification

Veryl: A Modern Hardware Description Language

Redis compatible server framework for Go

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Yet another Japanese IME for IBus/Linux

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

Bazel rules for Xilinx Vivado

Hardware definition language that compiles to Verilog

XLS: Accelerated HW Synthesis

EXPERIMENTAL high-level synthesizer from Scala 3

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges off-chip and creates high-level APIs using the type data.

Go language library for reading and writing Microsoft Excel™ (XLAM / XLSM / XLSX / XLTM / XLTX) spreadsheets

Brainf*ck machine written in Karuta

Network on Chip Implementation written in SytemVerilog

SystemVerilog parser library fully compliant with IEEE 1800-2017

Code generation tool for control and status registers

Verilog AXI components for FPGA implementation

Simple baseline JPEG decoder

An open-source static random access memory (SRAM) compiler.

30秒間の間にアイドルの女の子がいいねを集めるゲームです

Watsonを使ってサークルクラッシャーとお話したり、サークルクラッシャーになりきって会話相手を落とすゲーム

A multilingual input method framework

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the fut…

Cartographer is a system that provides real-time simultaneous localization and mapping (SLAM) in 2D and 3D across multiple platforms and sensor configurations.

Iroha for ruby

Polyphony is Python based High-Level Synthesis compiler.

An Open Source Machine Learning Framework for Everyone

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