A SpinalHDL project that outputs I2S signals on a Lattice iCEstick

AES-128 mutual authentication chip for the LAYR NFC access-control challenge — IHP SG13G2 130 nm, LibreLane tapeout

IHP SG13CMOS5L PDK

Plugin to generate BOM + CPL files for JLCPCB, assigning LCSC part numbers directly from the plugin, query the JLCPCB parts database, lookup datasheets and much more.

The LAYR files.

Workpackage 3 in OCDCpro - Teach the Teacher and Curriculum

Workpackage 5 in OCDCpro - Demonstrator with a 130nm microchip

Workpackage 2 in OCDCpro - Specification and verification of an open-source chip design toolchain

Home of the open-source EDA course.

Repository containing ULX3S blink LED binaries

A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

An attempt to recreate maimai gameplay within osu!lazer

LMN-3 DAW

LMN-3 DAW

Information, schematics and software for modular synths

130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:

Logic Analyzer IP Core

Bare-metal software for the Carbon1 RISC-V tape-out

Code for the paper "Agile Acceleration of Stateful Hash-Based Signatures in Hardware"

A full verilog workbench using: Icarus verilog, Cocotb, Yosys, gtkwave

riscv64 d1-nezha baremeta(Allwinner D1 riscv chip)

An evolving blockchain for prediction markets and futarchy.

A library for quantum processing units (IBM, D-Wave)

Community-driven community

Ease RiscV hardware-software co-design development by easily setting up or using a pre-configured environment

A SPHINCS+ implementation in the hardware description language SpinalHDL

Architecture for Embedded Graphical Interfaces

Custom Coprocessor Interface for VexRiscv