Browse, view and share your Claude Code sessions - runs entirely in browser 浏览和查看您的 Claude Code 会话历史 - 完全在浏览器中运行，无需服务器

Open Logic FPGA Standard Library

使用AI大模型，一键生成高清故事短视频。Generate high-definition story short videos with one click using AI large models.

国产VU13P加速卡资料

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Must-have verilog systemverilog modules

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Adafruit library for the 1.27" and 1.5" color OLEDs in the shop

Learning FPGA, yosys, nextpnr, and RISC-V

TMR utilities for the SpyDrNet project

This project aims to implement a TMR (Triple Modular Redundancy) solution on Xilinx FPGAs.

RSA attack tool (mainly for ctf) - retrieve private key from weak public key and/or uncipher data

IEEE P1735 decryptor for VHDL

SGMII

Opensource DDR3 Controller

A DDR3 memory controller in Verilog for various FPGAs

FT2232D emulator

Various kinds of "Clock Domain Crossing" synchronizers implmented in Verilog

HDL libraries and projects

Verilog Ethernet components for FPGA implementation

NetFPGA 1G CML Live development repository

Open source FPGA-based NIC and platform for in-network compute

A very simple and easy to understand RISC-V core.

Python library for SerDes modelling

PCI_Express总线经典书籍

Implementation of the PCIe physical layer

PCIE 5.0 Graduation project (Verification Team)

A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)