default search action
ACM Great Lakes Symposium on VLSI 2023: Knoxville, TN, USA
- Himanshu Thapliyal, Ronald F. DeMara, Inna Partin-Vaisband, Srinivas Katkoori:
Proceedings of the Great Lakes Symposium on VLSI 2023, GLSVLSI 2023, Knoxville, TN, USA, June 5-7, 2023. ACM 2023
Keynote I
- Niraj K. Jha
:
Smart Healthcare. 1
Session 1A: VLSI for Machine LearningVLSI for Machine Learning and Artificial Intelligence I
- Mehrdad Morsali
IMA-GNN: In-Memory Acceleration of Centralized and Decentralized Graph Neural Networks at the Edge. 3-8 - Jing Zhang
Low-Cost Multiple-Precision Multiplication Unit Design For Deep Learning. 9-14 - Salma Afifi
TRON: Transformer Neural Network Acceleration with Non-Coherent Silicon Photonics. 15-21
Session 1B: VLSI Circuits and Design I
- Qilin Si
PEPA: Performance Enhancement of Embedded Processors through HW Accelerator Resource Sharing. 23-28 - Yunkun Liao
Optimize the TX Architecture of RDMA NIC for Performance Isolation in the Cloud Environment. 29-35 - Hao Kong
KPU-SQL: Kernel Processing Unit for High-Performance SQL Acceleration. 37-43
Session 2A: Hardware Security I
- Pascal Nasahl
SCRAMBLE-CFI: Mitigating Fault-Induced Control-Flow Attacks on OpenTitan. 45-50 - Hanqiu Wang
HT-EMIS: A Deep Learning Tool for Hardware Trojan Detection and Identification through Runtime EM Side-Channels. 51-56 - Yankun Zhu
Exploring Remote Power Attacks Targeting Parallel Data Encryption On Multi-Tenant FPGAs. 57-62
Session 2B: VLSI Circuits and Design II
- Mohammad Munzurul Islam
Stochastically Pruning Large Language Models Using Sparsity Regularization and Compressive Sensing. 63-68 - Haishuang Fan
M2VT: A Multi-Output Encoder Accelerator for Multiple-Way Video Transcoding. 69-75 - Jiangnan Yu
TPNoC: An Efficient Topology Reconfigurable NoC Generator. 77-82
Keynote II
- Fred Chong
Closing the Gap between Quantum Algorithms and Machines with Hardware-Software Co-Design. 83-84
Special Session 1: Smart Healthcare Technologies
- Rajdeep Kumar Nath
Towards Self-Supervised Learning of ECG Signal Representation for the Classification of Acute Stress Types. 85-90 - Sushil Kumar Jain
OTFT Based Biosensor for Detection of Breast Cancer Biomarker (C-erbB-2). 91-96 - Musharraf N. Alruwaill
hChain: Blockchain Based Healthcare Data Sharing with Enhanced Security and Privacy Location-Based-Authentication. 97-102 - Md. Saif Hassan Onim
CASD-OA: Context-Aware Stress Detection for Older Adults with Machine Learning and Cortisol Biomarker. 103-108
Special Session 2: Quantum from Circuits and Algorithms to Systems and Applications
- Amisha Srivastava
Search Space Reduction for Efficient Quantum Compilation. 109-114 - Mohamed I. Ibrahim
Scalable Hybrid CMOS-Diamond Quantum Magnetometers. 115-116 - Jalil Morris
Fingerprinting Quantum Computer Equipment. 117-123 - Bhaskar Gaur
A Logarithmic Depth Quantum Carry-Lookahead Modulo (2n - 1) Adder. 125-130
Special Session 3: Emerging Technologies in Neuromorphic Computing
- Manu Rathore
Reliability Analysis of Memristive Reservoir Computing Architecture. 131-136 - Abhishek Moitra
Hardware Accelerators for Spiking Neural Networks for Energy-Efficient Edge Computing. 137-138 - Maryam Parsa
A Brain-inspired Approach for Malware Detection using Sub-semantic Hardware Features. 139-142 - Md. Mazharul Islam
A Cryogenic Artificial Synapse based on Superconducting Memristor. 143-148
Poster Session 1
- Md. Abdullah-Al Kaiser
A Context-Switching/Dual-Context ROM Augmented RAM using Standard 8T SRAM. 149-153 - Shivani Shah
MCSim: A Multi-Core Cache Simulator Accelerated on a Resource-constrained FPGA. 155-158 - Zhenlin Pei
Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect. 159-162 - Nitin D. Patwari
Design and Evaluation of Finite Field Multipliers Using Fast XNOR Cells. 163-166 - Aibin Yan, Shaojie Wei, Jinjun Zhang, Jie Cui, Jie Song, Tianming Ni, Patrick Girard, Xiaoqing Wen:
A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications. 167-171 - Haoyu Zhao
RBGC: Repurpose the Buffer of Fixed Graphics Pipeline to Enhance GPU Cache. 173-177 - Nishith N. Chakraborty
A Mixed-Signal Short-Term Plasticity Implementation for a Current-Controlled Memristive Synapse. 179-182 - Chen Nie, Xianjue Cai, Chenyang Lv, Chen Huang, Weikang Qian, Zhezhi He:
XMG-GPPIC: Efficient and Robust General-Purpose Processing-in-Cache with XOR-Majority-Graph. 183-187 - Yanjun Li
SRAM-Based Processing-In-Memory Design with Kullback-Leibler Divergence-Based Dynamic Precision Quantization. 189-192 - Najmeh Nazari
Inter-Layer Hybrid Quantization Scheme for Hardware Friendly Implementation of Embedded Deep Neural Networks. 193-196 - Upma Gandhi
RL-Ripper: : A Framework for Global Routing Using Reinforcement Learning and Smart Net Ripping Techniques. 197-201 - Sk Hasibul Alam
A Runtime-Reconfigurable Hardware Encoder for Spiking Neural Networks. 203-206 - Purab Ranjan Sutradhar
FlutPIM: : A Look-up Table-based Processing in Memory Architecture with Floating-point Computation Support for Deep Learning Applications. 207-211 - Samuel Dayo, Ataollah Saeed Monir, Mousa Karimi, Boris Vaisband:
Statistical Weight Refresh System for CTT-Based Synaptic Arrays. 213-214 - Tyler Cultice, Joseph Clark, Himanshu Thapliyal
Lightweight Hierarchical Root-of-Trust Framework for CAN-based 3D Printing Security. 215-216 - Raaga Sai Somesula
On Feasibility of Decision Trees for Edge Intelligence in Highly Constrained Internet-of-Things (IoT). 217-218 - Jing Zhang, Libo Huang, Hongbing Tan, Zhong Zheng, Hui Guo:
A Scalable BFloat16 Dot-Product Architecture for Deep Learning. 219-220 - Ling Yang
Confidence Counter Modelling for Value Predictor. 221-222 - Minjun Li:
Unaligned Access Optimization with Request-based Mapping Scheme for Solid-state Drives. 223-224 - Sercan Aygun
Reconvergent Path-aware Simulation of Bit-stream Processing. 225-226 - Debabrata Mondal, Syed Farah Naz, Ambika Prasad Shah:
Radiation Hardened and Leakage Power Attack Resilient 12T SRAM Cell for Secure Nuclear Environments. 227-228
Keynote III
- Mark M. Tehranipoor
Microelectronics Security in CHIPS Era. 229
Session 3A: IoT and Smart Systems
- Venkata K. V. V. Bathalapalli
PUFchain 4.0: Integrating PUF-based TPM in Distributed Ledger for Security-by-Design of IoT. 231-236 - Mallika Rathore
Precision and Performance-Aware Voltage Scaling in DNN Accelerators. 237-242 - Mohammadreza Mohammadi
Facial Expression Recognition at the Edge: CPU vs GPU vs VPU vs TPU. 243-248 - Seema G. Aarella
Fortified-Edge: Secure PUF Certificate Authentication Mechanism for Edge Data Centers in Collaborative Edge Computing. 249-254
Session 3B: Emerging Computing and Post-CMOS Technologies I
- Weiqing Ji
SOAER: Self-Obstacle Avoiding Escape Routing for Paper-Based Digital Microfluidic Biochips. 255-260 - Md. Oli-Uz-Zaman
Reconfigurable Mapping Algorithm based Stuck-At-Fault Mitigation in Neuromorphic Computing Systems. 261-266 - Okyanus T. Gumus
Digital LIF Neuron for CTT-Based Neuromorphic Systems. 267-272 - Sercan Aygun
Bit-Stream Processing with No Bit-Stream: Efficient Software Simulation of Stochastic Vision Machines. 273-279
Session 4A: Testing, Reliability, Fault-Tolerance
- Hritom Das
RFAM: RESET-Failure-Aware-Model for HfO2-based Memristor to Enhance the Reliability of Neuromorphic Design. 281-286 - Julian Höfer
SiFI-AI: A Fast and Flexible RTL Fault Simulation Framework Tailored for AI Models and Accelerators. 287-292 - Aibin Yan, Yang Chang, Jing Xiang, Hao Luo, Jie Cui, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen:
Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications. 293-298 - Yuyang Ye
FPGNN-ATPG: An Efficient Fault Parallel Automatic Test Pattern Generator. 299-304
Session 4B: Computer-Aided Design (CAD) I
- Lingjie Li
More Efficient Accuracy-Ensured Waveform Compression for Circuit Simulation Supporting Asynchronous Waveforms. 305-311 - Jhen-Gang Lin
DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network. 313-319 - Hwapyong Kim
Placement Legalization Amenable to Mixed-cell-height Standard Cells Integrating into State-of-the-art Commercial EDA Tool. 321-326 - Qilin Si
ADVICE: Automatic Design and Optimization of Behavioral Application Specific Processors. 327-332
Special Session 4: Machine Learning and Hardware Security: A Winning Combo!
- Dake Chen
Island-based Random Dynamic Voltage Scaling vs ML-Enhanced Power Side-Channel Attacks. 333-338 - Yeganeh Aghamohammadi
CoLA: Convolutional Neural Network Model for Secure Low Overhead Logic Locking Assignment. 339-344 - Kaveh Shamsi
Enhancing Solver-based Generic Side-Channel Analysis with Machine Learning. 345-350 - Hongye Xu
Exploiting Logic Locking for a Neural Trojan Attack on Machine Learning Accelerators. 351-356
Poster Session 2
- Xinshi Zang
CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems. 357-361 - Syuan-Han Liang
Hybrid-Row-Height Design Placement Legalization Considering Cell Variants. 363-367 - Mengshi Gong
An Efficient and Robust Algorithm for Common Path Pessimism Removal In Static Timing Analysis. 369-372 - Zhenyi Gao
Efficient and Effective Digital Waveform Compression for Large-scale Logic Simulation of Integrated Circuit. 373-377 - Duo Wang
A High-accurate Multi-objective Ensemble Exploration Framework for Design Space of CPU Microarchitecture. 379-383 - Sheng Xu
DrPIM: An Adaptive and Less-blocking Data Replication Framework for Processing-in-Memory Architecture. 385-389 - Chun-Wei Chiu
A Macro Legalization Approach Considering Minimum Channel Spacing and Buffer Area Reservation Constraints. 391-395 - Mohsen Riahi Alam
Stochastic Computing for Reliable Memristive In-Memory Computation. 397-401 - Hadi Noureddine
High-Density FeFET-based CAM Cell Design Via Multi-Dimensional Encoding. 403-407 - Rajat Bhattacharjya
Locate: Low-Power Viterbi Decoder Exploration using Approximate Adders. 409-413 - Travis LeCompte
Graph Neural Network Assisted Quantum Compilation for Qubit Allocation. 415-419 - Rassul Bairamkulov
Compound Logic Gates for Pipeline Depth Minimization in Single Flux Quantum Integrated Systems. 421-425 - Bhaskar Gaur
Noise-Resilient and Reduced Depth Approximate Adders for NISQ Quantum Computing. 427-431 - Kaixuan Wang
SVP: Safe and Efficient Speculative Execution Mechanism through Value Prediction. 433-437 - Thai-Ha Tran
Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks. 439-442 - Zachary J. Ellis
RAGA: Resource-Aware Tree-Splitting for High Performance Knuth-Yao-based Discrete Gaussian Sampling on FPGAs. 443-447 - Yang Ni
Efficient Off-Policy Reinforcement Learning via Brain-Inspired Computing. 449-453 - Hung-Yang Chang
High-Throughput Edge Inference for BERT Models via Neural Architecture Search and Pipeline. 455-459 - Adewale Adeyemo
Enhancing the Security of Collaborative Deep Neural Networks: An Examination of the Effect of Low Pass Filters. 461-465 - Xiaotian Zhao
Design Space Exploration of Layer-Wise Mixed-Precision Quantization with Tightly Integrated Edge Inference Units. 467-471 - Sai Karthik Nandigama
EBASA: Error Balanced Approximate Systolic Array Architecture Design. 473-476 - Nicola Dall'Ora
Verilog-A Implementation of Generic Defect Templates for Analog Fault Injection. 477-481
Session 5A: VLSI for Machine Learning and Artificial Intelligence II
- Weiqing Ji
GAT-based Concentration Prediction for Random Microfluidic Mixers with Multiple Input Flow Rates. 483-488 - Lingxiang Yin
Exploring Architecture, Dataflow, and Sparsity for GCN Accelerators: A Holistic Framework. 489-495 - Sepehr Tabrizchi
SenTer: A Reconfigurable Processing-in-Sensor Architecture Enabling Efficient Ternary MLP. 497-502 - Bindu G. Gowda
IMAC: : A Pre-Multiplier And Integrated Reduction Based Multiply-And-Accumulate Unit. 503-508
Session 5B: Emerging Computing and Post-CMOS Technologies II
- Debraj Kundu
Reinforcement Learning based Module Placement for Enhancing Reliability of MEDA Digital Microfluidic Biochips. 509-514 - Xinda Chen
JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits. 515-520 - Arun Govindankutty
Ternary In-Memory Computing with Cryogenic Quantum Anomalous Hall Effect Memories. 521-526 - Ming Han
ATC: Approximate Temporal Coding for Efficient Implementations of Spiking Neural Networks. 527-532
Special Session 5: Optical Computing for Emerging VLSI Systems
- Amin Shafiee
Design Space Exploration for PCM-based Photonic Memory. 533-538 - Febin Sunny
Cross-Layer Design for AI Acceleration with Non-Coherent Optical Computing. 539-544 - Ishan G. Thakkar
High-Speed and Energy-Efficient Non-Binary Computing with Polymorphic Electro-Optic Circuits and Architectures. 545-550 - Kaveh (Hassan) Rahbardar Mojaver
Multi-Transverse-Mode Silicon Photonics for Quantum Computing. 551-556
Session 6A: Hardware Security II
- Shayan Moini
Fault Recovery from Multi-Tenant FPGA Voltage Attacks. 557-562 - Preet Derasari
MAYAVI: A Cyber-Deception Hardware for Memory Load-Stores. 563-568 - Yadi Zhong
On-Demand Device Authentication using Zero-Knowledge Proofs for Smart Systems. 569-574 - Priya Mittu
TimingCamouflage+ Decamouflaged. 575-580
Session 6B: Computer-Aided Design (CAD) II
- Yan Pi
ESFO: Equality Saturation for FIRRTL Optimization. 581-586 - Joseph Clark
TDAG: Tree-based Directed Acyclic Graph Partitioning for Quantum Circuits. 587-592 - Xinshi Zang
SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems. 593-598 - Manfred Schlägl
GUI-VP Kit: A RISC-V VP Meets Linux Graphics - Enabling Interactive Graphical Application Development. 599-605
Special Session 6: Efficient In-Memory and In-Sensor Computing Platforms
- Mohammed E. Elbtity
Heterogeneous Integration of In-Memory Analog Computing Architectures with Tensor Processing Units. 607-612 - Md. Abdullah-Al Kaiser
Technology-Circuit-Algorithm Tri-Design for Processing-in-Pixel-in-Memory (P2M). 613-618 - Abhiroop Bhattacharjee
Examining the Role and Limits of Batchnorm Optimization to Mitigate Diverse Hardware-noise in In-memory Computing. 619-624 - Nakul Kochar
Accelerating Low Bit-width Neural Networks at the Edge, PIM or FPGA: A Comparative Study. 625-630
Session 7A: VLSI Circuits and Design III
- Adou Sangbone Assoa
A Scalable Platform for Single-Snapshot Direction Of Arrival (DOA) Estimation in Massive MIMO Systems. 631-637 - James Oelund
ILAFD: Accuracy-Configurable Floating-Point Divider Using an Approximate Reciprocal and an Iterative Logarithmic Multiplier. 639-644 - Aditya Anirudh Jonnalagadda
Design of Energy Efficient Posit Multiplier. 645-651 - Sudeep Pasricha
Ethics in Computing Education: Challenges and Experience with Embedded Ethics. 653-658
Session 7B: Emerging Computing and Post-CMOS Technologies III
- Md Hasibul Amin
IMAC-Sim: : A Circuit-level Simulator For In-Memory Analog Computing Architectures. 659-664 - Jie Lou
Scalable Time-Domain Compute-in-Memory BNN Engine with 2.06 POPS/W Energy Efficiency for Edge-AI Devices. 665-670 - Salim Ullah
CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators. 671-677 - Alain Aoun
A Machine Learning Based Load Value Approximator Guided by the Tightened Value Locality. 679-684
Special Session 7: Machine Learning and Reconfigurability: Towards Sustainable Security
- Mohammad Sazadur Rahman
Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic Locking. 685-690 - Martin Manuel Lopez
Machine Learning for Intrusion Detection: Stream Classification Guided by Clustering for Sustainable Security in IoT. 691-696 - Kaniz Mishty
System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning. 697-702 - Md Toufiq Hasan Anik
Aging-Induced Failure Prognosis via Digital Sensors. 703-708
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-04 20:31 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: