default search action
45th ISCA 2018: Los Angeles, CA, USA
- Murali Annavaram, Timothy Mark Pinkston, Babak Falsafi:
45th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2018, Los Angeles, CA, USA, June 1-6, 2018. IEEE Computer Society 2018, ISBN 978-1-5386-5984-7
Session 1A: Clouds & Datacenters
- Jeremy Fowers, Kalin Ovtcharov, Michael Papamichael, Todd Massengill, Ming Liu, Daniel Lo, Shlomi Alkalay, Michael Haselman, Logan Adams, Mahdi Ghandi, Stephen Heil, Prerak Patel, Adam Sapek
, Gabriel Weisz, Lisa Woods, Sitaram Lanka, Steven K. Reinhardt, Adrian M. Caulfield, Eric S. Chung, Doug Burger:
A Configurable Cloud-Scale DNN Processor for Real-Time AI. 1-14 - Matt Skach, Manish Arora, Dean M. Tullsen
Virtual Melting Temperature: Managing Server Load to Minimize Cooling Overhead with Phase Change Materials. 15-28 - Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. 29-42
Session 1B: Accelerators for Emerging Apps
- Prakalp Srivastava, Mingu Kang, Sujan K. Gonugondla
PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms. 43-56 - Marc Riera, José-María Arnau, Antonio González:
Computation Reuse in DNNs by Exploiting Input Similarity. 57-68 - Daichi Fujiki
GenAx: A Genome Sequencing Accelerator. 69-82
Session 2A: Prefetching
- Sushant Kondguli, Michael C. Huang
Division of Labor: A More Effective Approach to Prefetching. 83-95 - Anant Nori, Jayesh Gaur, Siddharth Rai
Criticality Aware Tiered Cache Hierarchy: A Fundamental Relook at Multi-Level Cache Hierarchies. 96-109 - Akanksha Jain, Calvin Lin:
Rethinking Belady's Algorithm to Accommodate Prefetching. 110-123
Session 2B: Languages & Models
- Sizhuo Zhang, Muralidaran Vijayaraghavan
Constructing a Weak Memory Model. 124-137 - Martin Maas, Krste Asanovic, John Kubiatowicz:
A Hardware Accelerator for Tracing Garbage Collection. 138-151 - Weilong Cui, Yongshan Ding
Charm: A Language for Closed-Form High-Level Architecture Modeling. 152-165
Session 3A: Virtual Memory
- Yuxi Liu, Xia Zhao, Magnus Jahre
Get Out of the Valley: Power-Efficient Address Mapping for GPUs. 166-179 - Seunghee Shin, Guilherme Cox
Scheduling Page Table Walks for Irregular GPU Applications. 180-192 - Mayank Parasar, Abhishek Bhattacharjee
SEESAW: Using Superpages to Improve VIPT Caches. 193-206 - Nandita Vijaykumar, Abhilasha Jain, Diptesh Majumdar, Kevin Hsieh
A Case for Richer Cross-Layer Abstractions: Bridging the Semantic Gap with Expressive Memory. 207-220
Session 3B: Coherence & Memory Ordering
- Alberto Ros
Non-Speculative Store Coalescing in Total Store Order. 221-234 - Zhaoxiang Jin, Soner Önder:
Dynamic Memory Dependence Predication. 235-246 - Nicolai Oswald, Vijay Nagarajan
ProtoGen: Automatically Generating Directory Cache Coherence Protocols from Atomic Specifications. 247-260 - Johnathan Alsop, Matthew D. Sinclair, Sarita V. Adve:
Spandex: A Flexible Interface for Efficient Heterogeneous Coherence. 261-274
Session 4A: Emerging Paradigms
- Dayeol Lee, Gwangmu Lee, Dongup Kwon, Sunghwa Lee, Youngsok Kim
Flexon: A Flexible Digital Neuron for Efficient Spiking Neural Network Simulations. 275-288 - James E. Smith:
Space-Time Algebra: A Model for Neocortical Computation. 289-300 - Xiangyu Zhang, Ramin Bashizade, Craig LaBoda, Chris Dwyer, Alvin R. Lebeck:
Architecting a Stochastic Computing Unit with Molecular Optical Devices. 301-314
Session 4B: Persistence
- Kunal Korgaonkar, Ishwar Bhati, Huichu Liu, Jayesh Gaur, Sasikanth Manipatruni, Sreenivas Subramoney
Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache. 315-327 - Vinson Young, Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction. 328-339 - Fengbin Tu
RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM. 340-352
Session 5A: Emerging Memory 1
- Adi Fuchs, David Wentzlaff:
Scaling Datacenter Accelerators with Compute-Reuse Architectures. 353-366 - Ben Feinberg, Uday Kumar Reddy Vengalam, Nathan Whitehair, Shibo Wang, Engin Ipek:
Enabling Scientific Computing on Memristive Accelerators. 367-382 - Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Ravi R. Iyer, Dennis Sylvester, David T. Blaauw, Reetuparna Das:
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks. 383-396
Session 5B: Storage
- Arash Tavakkol, Mohammad Sadrosadati, Saugata Ghose, Jeremie S. Kim, Yixin Luo, Yaohua Wang, Nika Mansouri-Ghiasi, Lois Orosa
FLIN: Enabling Fairness and Enhancing Performance in Modern NVMe Solid State Drives. 397-410 - Sang Woo Jun
GraFBoost: Using Accelerated Flash Storage for External Graph Analytics. 411-424 - Duck-Ho Bae, Insoon Jo, Youra Choi, Joo Young Hwang, Sangyeun Cho, Daniel D. G. Lee, Jaeheon Jeong:
2B-SSD: The Case for Dual, Byte- and Block-Addressable Solid-State Drives. 425-438
Session 6A: Emerging Memory 2
- Mohammad A. Alshboul
Lazy Persistency: A High-Performing and Write-Efficient Software Persistency Technique. 439-451 - Arpit Joshi, Vijay Nagarajan
DHTM: Durable Hardware Transactional Memory. 452-465 - Tiancong Wang, Sakthikumaran Sambasivam, James Tuck
Hardware Supported Permission Checks on Persistent Objects for Performance and Programmability. 466-478
Session 6B: Controllers & Control Systems
- Jacob Sacks
RoboX: An End-to-End Solution to Accelerate Autonomous Control in Robotics. 479-490 - Dongup Kwon, Jaehyung Ahn, Dongju Chae, Mohammadamin Ajdari, Jaewon Lee, Suheon Bae, Youngsok Kim
DCS-ctrl: A Fast and Flexible Device-Control Mechanism for Device-Centric Server Architecture. 491-504 - Raghavendra Pradyumna Pothukuchi
Yukta: Multilayer Resource Controllers to Maximize Efficiency. 505-518
Session 7A: Mobile Platforms
- Samira Mirbagher Ajorpaz
Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer. 519-532 - Mark Buckler, Philip Bedoukian, Suren Jayasuriya, Adrian Sampson
EVA2: Exploiting Temporal Redundancy in Live Computer Vision. 533-546 - Yuhao Zhu, Anand Samajdar, Matthew Mattina, Paul N. Whatmough:
Euphrates: Algorithm-SoC Co-Design for Low-Power Mobile Continuous Vision. 547-560 - Woo-Seok Choi, Matthew Tomei, Jose Rodrigo Sanchez Vicarte
Guaranteeing Local Differential Privacy on Ultra-Low-Power Systems. 561-574 - Cheng Tan
Stitch: Fusible Heterogeneous Accelerators Enmeshed with Many-Core Architecture for Wearables. 575-587
Session 7B: Security
- Kate Nguyen, Kehan Lyu, Xianze Meng, Vilas Sridharan, Xun Jian
Nonblocking Memory Refresh. 588-599 - Kanad Sinha, Simha Sethumadhavan:
Practical Memory Safety with REST. 600-611 - Seyed Mohammad Seyedzadeh, Alex K. Jones
Mitigating Wordline Crosstalk Using Adaptive Trees of Counters. 612-623 - Mohammadkazem Taram, Ashish Venkat
Mobilizing the Micro-Ops: Exploiting Context Sensitive Decoding for Security and Energy Efficiency. 624-637 - Alric Althoff, Joseph McMahan, Luis Vega, Scott Davidson, Timothy Sherwood
Hiding Intermittent Information Leakage with Architectural Support for Blinking. 638-649
Session 8A: Machine Learning Systems 1
- Amir Yazdanbakhsh
GANAX: A Unified MIMD-SIMD Acceleration for Generative Adversarial Networks. 650-661 - Vahideh Akhlaghi, Amir Yazdanbakhsh
SnaPEA: Predictive Early Activation for Reducing Computation in Deep Convolutional Neural Networks. 662-673 - Kartik Hegde, Jiyong Yu
UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition. 674-687 - Eunhyeok Park, Dongyoung Kim, Sungjoo Yoo:
Energy-Efficient Neural Network Accelerator Based on Outlier-Aware Low-Precision Computation. 688-698
Session 8B: Interconnection Networks
- Aniruddh Ramrakhyani, Paul V. Gratz
Synchronized Progress in Interconnection Networks (SPIN): A New Theory for Deadlock Freedom. 699-711 - Gwangsun Kim
TCEP: Traffic Consolidation for Energy-Proportional High-Radix Networks. 712-725 - Jieming Yin, Zhifeng Lin, Onur Kayiran, Matthew Poremba, Muhammad Shoaib Bin Altaf, Natalie D. Enright Jerger
Modular Routing Design for Chiplet-Based Systems. 726-738 - Nachiket Kapre, Tushar Krishna:
FastTrack: Leveraging Heterogeneous FPGA Wires to Design Low-Cost High-Performance Soft NoCs. 739-751
Session 9A: Machine Learning Systems 2
- Mingcong Song, Jiechen Zhao, Yang Hu, Jiaqi Zhang, Tao Li:
Prediction Based Execution on Deep Neural Networks. 752-763 - Hardik Sharma, Jongse Park, Naveen Suda, Liangzhen Lai, Benson Chau, Vikas Chandra, Hadi Esmaeilzadeh:
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network. 764-775 - Animesh Jain, Amar Phanishayee, Jason Mars, Lingjia Tang, Gennady Pekhimenko:
Gist: Efficient Data Encoding for Deep Neural Network Training. 776-789 - Reza Yazdani, Marc Riera, José-María Arnau, Antonio González:
The Dark Side of DNN Pruning. 790-801
Session 9B: GPUs
- Bhargava Gopireddy, Dimitrios Skarlatos, Wenjuan Zhu
HetCore: TFET-CMOS Hetero-Device Architecture for CPUs and GPUs. 802-815 - Farzad Khorasani, Hodjat Asghari Esfeden, Amin Farmahini Farahani, Nuwan Jayasena, Vivek Sarkar:
RegMutex: Inter-Warp GPU Register Time-Sharing. 816-828 - Nandita Vijaykumar, Eiman Ebrahimi, Kevin Hsieh
The Locality Descriptor: A Holistic Cross-Layer Abstraction to Express Data Locality In GPUs. 829-842 - Ján Veselý, Arkaprava Basu, Abhishek Bhattacharjee
Generic System Calls for GPUs. 843-856
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-05-08 00:50 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: