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ISSCC 2023: San Francisco, CA, USA
- IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023. IEEE 2023, ISBN 978-1-6654-9016-0
- Laura Chizuko Fujino:
Reflections. 4 - Piet Wambacq:
Foreword: Building on 70 Years of Innovation in Solid-State Circuit Design. 5 - Lisa Su, Sam Naffziger:
Innovation For the Next Decade of Compute Efficiency. 8-12 - Akira Matsuzawa:
Shape the World with Mixed-Signal Integrated Circuits - Past, Present, and Future. 13-22 - Jo De Boeck, Jean-René Léquepeys, Christoph Kutter:
EU Ships Act Drives Pan-European Full-Stack Innovation Partnerships. 26-32 - Erik Ekudden:
5G Drives Exponential Increase in Processing Needs Across all Industries. 33-35 - Benjamin Munger, Kathy Wilcox, Jeshuah Sniderman, Chuck Tung, Brett Johnson, Russell Schreiber, Carson Henrion, Kevin Gillespie, Tom Burd, Harry R. Fair III, Dave Johnson, Jonathan White, Scott McLelland, Steven Bakke, Javin Olson, Ryan McCracken, Matthew Pickett, Aaron Horiuchi, Hien Nguyen, Tim Jackson:
"Zen 4": The AMD 5nm 5.7GHz x86-64 Microprocessor Core. 38-39 - Bo-Jr Huang, Alfred Tsai, Lear Hsieh, Kathleen Chang, C.-J. Tsai, Jia-Ming Chen, Eric Jia-Wei Fang, Sung S.-Y. Hsueh, Jack Ciao, Barry Chen, Chuck Chang, Ping Kao, Ericbill Wang, Harry H. Chen, Hugh Mair, Shih-Arn Hwang:
A 5G Mobile Gaming-Centric SoC with High-Performance Thermal Management in 4nm FinFET. 40-41 - Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Arias
, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura:
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension. 42-43 - Yen-Lung Chen, Chung-Hsuan Yang, Yi-Chung Wu
A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing. 44-45 - I-Ting Lin, Zih-Sing Fu, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang:
A 28nm 142mW Motion-Control SoC for Autonomous Mobile Robots. 46-47 - Kai-Ping Lin, Jia-Han Liu, Jyun-Yi Wu, Hong-Chuan Liao, Chao-Tsung Huang:
VISTA: A 704mW 4K-UHD CNN Processor for Video and Image Spatial/Temporal Interpolation Acceleration. 48-49 - Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Hoi-Jun Yoo:
MetaVRain: A 133mW Real-Time Hyper-Realistic 3D-NeRF Processor with 1D-2D Hybrid-Neural Engines for Metaverse on Mobile Devices. 50-51 - Huajun Zhang
A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier. 54-55 - Thije Rooijers, Johan H. Huijsing, Kofi A. A. Makinwa:
A Chopper-Stabilized Amplifier with a Relaxed Fill-In Technique and 22.6pA Input Current. 56-57 - Subha Sarkar, Rajat Agarwal, Nagendra Krishnapura:
Bandpass Filter and Oscillator ICs with THD ppd for Testing High-Resolution ADCs. 58-59 - Xiaomeng An, Sining Pan, Hui Jiang, Kofi A. A. Makinwa:
A 0.01 mm2 10MHz RC Frequency Reference with a 1-Point On-Chip-Trimmed Inaccuracy of $\boldsymbol{\pm 0.28\%}$ from $\boldsymbol{-45^{\mathrm{o}}\mathrm{C}}$ to $\boldsymbol{125^{\mathrm{o}}\mathrm{C}}$ in 0.18μm CMOS. 60-61 - Kyu-Sang Park
A $1.4\mu$ W/MHz 100MHz RC Oscillator with $\pm$ 1030ppm Inaccuracy from $-40^{\circ}\mathrm{C}$ to $85^{\circ}\mathrm{C}$ After Accelerated Aging for 500 Hours at $125^{\circ}\mathrm{C}$. 62-63 - Haihua Li, Ka-Meng Lei, Pui-In Mak, Rui Paulo Martins:
A 12/13.56MHz Crystal Oscillator with Binary-Search-Assisted Two-Step Injection Achieving 5.0nJ Startup Energy and 45.8μs Startup Time. 64-65 - Zhikuang Cai, Xin Wang
A 16MHz X0 with 17.5μs Startup Time Under 104ppm-ΔF Injection Using Automatic Phase-Error Correction Technique. 66-67 - Yihan Zhang, You You, Wenjie Ren
A 0.954nW 32kHz Crystal Oscillator in 22nm CMOS with Gm-C-Based Current Injection Control. 68-69 - Subhashish Mukherjee, Yogesh Darwhekar, Jayawardan Janardhanan, Peeyoosh Mirajkar, Raghavendra Reddy, Harish Ramesh, Bichoy Bahr, Jagdish Chand, Uday Meda, Baher Haroun, Shankar Karantha, Ernest Ting-Ta Yen, Keegan Martin, Daniel Gan, Amin Sijelmassi, Sankaran Aniruddhan:
A 0.5-to-400MHz Programmable BAW Oscillator with Fractional Output Divider Achieving 4ppm Frequency Stability over Temperature and <95fs Jitter. 70-71 - Pratap Tumkur Renukaswamy, Kristof Vaesen, Nereo Markulic, Veerle Derudder, Dae-Woong Park, Piet Wambacq, Jan Craninckx:
A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL. 74-75 - Yongwoo Jo
A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier. 76-77 - Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Luca Lanzoni, Michele Rossoni
A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. 78-79 - Junjun Qiu, Wenqian Wang, Zheng Sun, Bangan Liu, Yuncheng Zhang, Dingxin Xu, Hongye Huang
A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration. 80-81 - Giacomo Castoro, Simone Mattia Dartizio, Francesco Tesolin, Francesco Buccoleri, Michele Rossoni
A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology. 82-83 - Jooeun Bang
A $47\text{fs}_{\text{rms}}$-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth. 84-85 - Zhao Zhang, Xinyu Shen, Zhaoyu Zhang, Guike Li, Nan Qi, Jian Liu, Yong Chen, Nanjian Wu, Liyuan Liu:
A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur. 86-87 - Menghan Guo, Shoushun Chen, Zhe Gao, Wenlei Yang, Peter Bartkovjak, Qing Qin, Xiaoqin Hu, Dahei Zhou, Masayuki Uchiyama, Shimpei Fukuoka, Chengcheng Xu, Hiroaki Ebihara, Andy Wang, Peiwen Jiang, Bo Jiang, Bo Mu, Huan Chen, Jason Yang, TJ Dai, Andreas Suess, Yoshiharu Kudo:
A 3-Wafer-Stacked Hybrid 15MPixel CIS + 1 MPixel EVS with 4.6GEvent/s Readout, In-Pixel TDC and On-Chip ISP and ESP Function. 90-91 - Kazutoshi Kodama, Yusuke Sato, Yuhi Yorikado, Raphael Berner, Kyoji Mizoguchi, Takahiro Miyazaki, Masahiro Tsukamoto, Yoshihisa Matoba, Hirotaka Shinozaki, Atsumi Niwa, Tetsuji Yamaguchi, Christian Brandli, Hayato Wakabayashi, Yusuke Oike:
1.22μm 35.6Mpixel RGB Hybrid Event-Based Vision Sensor with 4.88μm-Pitch Event Pixels and up to 10K Event Frame Rate by Adaptive Control on Event Sparsity. 92-93 - Atsumi Niwa, Futa Mochizuki, Raphael Berner, Takuya Maruyarma, Toshio Terano, Kenichi Takamiya, Yasutaka Kimura, Kyoji Mizoguchi, Takahiro Miyazaki, Shun Kaizu, Hirotsugu Takahashi, Atsushi Suzuki, Christian Brandli, Hayato Wakabayashi, Yusuke Oike:
A 2.97μm-Pitch Event-Based Vision Sensor with Shared Pixel Front-End Circuitry and Low-Noise Intensity Readout Mode. 94-95 - Hyuncheol Kim, Yun Hyeok Kim, Sanghyuck Moon, Hwanwoong Kim, Byeongjun Yoo, Jueun Park, Seyoung Kim, June-Mo Koo, Sewon Seo, Hye Ji Shin, Younghwan Choi, Jinwoo Kim, Kyungil Kim, Jae-Hoon Seo, Seunghyun Lim, Taesub Jung, Howoo Park, Sangil Jung, Juhyun Ko, Kyungho Lee, JungChak Ahn, Joonseo Yim:
A 0.64μm 4-Photodiode 1.28μm 50Mpixel CMOS Image Sensor with 0.98e- Temporal Noise and 20Ke- Full-Well Capacity Employing Quarter-Ring Source-Follower. 96-97 - Min Liu
A 16.4kPixel 3.08-to-3.86THz Digital Real-Time CMOS Image Sensor with 73dB Dynamic Range. 98-99 - Byungchoul Park, Byungwook Ahn, Hyun-Seung Choi, Jinwoong Jeong, Kangmin Hwang, Taewoo Kim, Myung-Jae Lee, Youngcheol Chae:
A 400 × 200 600fps 117.7dB-DR SPAD X-Ray Detector with Seamless Global Shutter and Time-Encoded Extrapolation Counter. 100-101 - Karim Ali Ahmed, Hayate Okuhara, Massimo Alioto:
55pW/pixel Peak Power Imager with Near-Sensor Novelty/Edge Detection and DC-DC Converter-Less MPPT for Purely Harvested Sensor Nodes. 102-103 - Rahul Gulve, Roberto Rangel, Ayandev Barman, Don Nguyen, Mian Wei, Motasem Sakr, Xiaonong Sun, David B. Lindell
Dual-Port CMOS Image Sensor with Regression-Based HDR Flux-to-Digital Conversion and 80ns Rapid-Update Pixel-Wise Exposure Coding. 104-105 - Bo Zhang, Anand Vasani, Ashutosh Sinha, Alireza Nilchi, Haitao Tong, Lakshmi P. Rao
A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology. 108-109 - Henry Park, Mohammed Abdullatif, Ehung Chen, Ahmed Elmallah, Qaiser Nehal, Miguel Gandara, Tsz-Bin Liu, Amr Khashaba, Joonyeong Lee, Chih-Yi Kuan, Dhinessh Ramachandran, Ruey-Bo Sun, Atharav Atharav, Yusang Chun, Mantian Zhang, Deng-Fu Weng, Chung-Hsien Tsai, Chen-Hao Chang, Chia-Sheng Peng, Sheng-Tsung Hsu, Tamer A. Ali:
A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET. 110-111 - Bingyi Ye, Guangdong Wu, Weixin Gai, Kai Sheng
A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS. 112-113 - Kihwan Seong, Donguk Park, Gyeom-Je Bae, Hyunwoo Lee, Youngseob Suh, Wooseuk Oh, Hyemun Lee, Juyoung Kim, Takgun Lee, Geonhoo Mo, Sukhyun Jung, Dongcheol Choi, Byoung-Joo Yoo, Sanghune Park, Hyo-Gyuem Rhew, Jongshin Shin:
A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques. 114-115 - Chien-Kai Kao, Shih-Che Hung, Tse-Hsien Yeh, Chen-Yu Hsiao:
A 37.8dB Channel Loss 0.6μs Lock Time CDR with Flash Frequency Acquisition in 5nm FinFET. 116-117 - Seungwoo Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Hyunsu Park, Youngwook Kwon, Chulwoo Kim:
A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications. 118-119 - Kai Sheng
A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS. 120-121 - Jeonghyu Yang, Eunji Song, Seungwook Hong, Dongjun Lee, Sangwan Lee, Hyunwoo Im, Tae-ho Shin, Jaeduk Han:
A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm. 122-123 - Ping-Chun Wu, Jian-Wei Su
A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices. 126-127 - An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang:
A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. 128-129 - Yifan He, Haikang Diao, Chen Tang, Wenbin Jia, Xiyuan Tang, Yuan Wang, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu:
A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference. 130-131 - Haruki Mori, Wei-Chang Zhao, Cheng-En Lee, Chia-Fu Lee, Yu-Hao Hsu, Chao-Kai Chuang, Takeshi Hashizume, Hao-Chun Tung, Yao-Yi Liu, Shin-Rung Wu, Kerem Akarvardar, Tan-Li Chou, Hidehiro Fujiwara, Yih Wang
A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update. 132-133 - Bo Wang, Chen Xue, Zhongyuan Feng, Zhaoyang Zhang, Han Liu, Lizheng Ren, Xiang Li, Anran Yin, Tianzhu Xiong, Yeyang Xue, Shengnan He, Yuyao Kong, Yongliang Zhou, An Guo, Xin Si, Jun Yang:
A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks. 134-135 - Sung-En Hsieh, Chun-Hao Wei, Cheng-Xin Xue, Hung-Wei Lin, Wei-Hsuan Tu, En-Jui Chang, Kai-Taing Yang, Po-Heng Chen, Wei-Nan Liao, Li Lian Low, Chia-Da Lee, Allen-Cl Lu, Jenwei Liang, Chih-Chung Cheng, Tzung-Hung Kang:
A 70.85-86.27TOPS/W PVT-Insensitive 8b Word-Wise ACIM with Post-Processing Relaxation. 136-137 - Zhiheng Yue, Yang Wang, Huizheng Wang
CV-CIM: A 28nm XOR-Derived Similarity-Aware Computation-in-Memory for Cost-Volume Construction. 138-139 - Peiyu Chen
A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing. 140-141 - Jooyoung Bae, Wonsik Oh, Jahyun Koo, Bongjin Kim:
CTLE-Ising:A 1440-Spin Continuous-Time Latch-Based isling Machine with One-Shot Fully-Parallel Spin Updates Featuring Equalization of Spin States. 142-143 - Qixiu Wu, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiwei Zhang, Zhihua Wang, Baoyong Chi:
An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique. 146-147 - Xiangxun Zhan, Jun Yin, Pui-In Mak, Rui Paulo Martins:
A 22.4-to-26.8GHz Dual-Path-Synchronized Quad-Core Oscillator Achieving -138dBc/Hz PN and 193.3dBc/Hz FoM at 10MHz Offset from 25.8GHz. 148-149 - Yiyang Shu, Zhixian Deng, Xun Luo:
A 28GHz Scalable Inter-Core-Shaping Multi-Core Oscillator with DM/CM-Configured Coupling Achieving 193.3dBc/Hz FoM and 205.5dBc/Hz FoMA at 1MHz Offset. 150-151 - Hao Guo, Yong Chen, Yunbo Huang, Pui-In Mak, Rui Paulo Martins:
An 83.3-to-104.7GHz Harmonic-Extraction VCO Incorporating Multi-Resonance, Multi-Core, and Multi-Mode (3M) Techniques Achieving -124dBc/Hz Absolute PN and 190.7dBc/Hz $\text{FoM}_{\mathrm{T}}$. 152-153 - Tim C. Fischer, Anantha Kumar Nivarti, Raghuvir Ramachandran, Ram Bharti, Derek Carson, Anton Lawrendra, Vineet Mudgal, Vivek Santhosh, Sunil Shukla, Te-Chen Tsai:
D1: A 7nm ML Training Processor with Wave Clock Distribution. 156-157 - David Garrett, Youn Sung Park, Seongjong Kim, Jay Sharma, Wenbin Huang, Majid Shaghaghi, Vinay Parthasarathy, Stephen Gibellini, Stephen Bailey, Mallik Moturi, Pieter Vorenkamp, Kurt Busch, Jeremy Holleman, Behrooz Javid, Alireza Yousefi, Mohsen Judy, Atul Gupta:
A 1mW Always-on Computer Vision Deep Learning Neural Decision Processor. 158-159 - Ying Wei, Yi Chieh Huang, Haiming Tang, Nithya Sankaran, Ish Chadha, Dai Dai, Olakanmi Oluwole, Vishnu Balan, Edward Lee:
NVLink-C2C: A Coherent Off Package Chip-to-Chip Interconnect with 40Gbps/pin Single-ended Signaling. 160-161 - Naru Sundar, Brad Burres, Yadong Li, Dave Minturn, Brian Johnson, Nupur Jain:
An In-depth Look at the Intel IPU E2000. 162-163 - Sung-En Hsieh, Tzu-Chien Wu, Chun-Chih Hou:
A 1.8GHz 12b Pre-Sampling Pipelined ADC with Reference Buffer and OP Power Relaxations. 166-167 - Junyan Hao, Minglei Zhang, Yanbo Zhang, Shubin Liu, Zhangming Zhu, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness. 168-169 - Yuefeng Cao
A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer. 170-171 - Manxin Li, Calvin Yoji Lee, Ahmed ElShater, Yuichi Miyahara, Kazuki Sobue, Koji Tomioka, Un-Ku Moon:
A Rail-to-Rail 12MS 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting. 172-173 - Hongshuai Zhang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
A 25MHz-BW 77.2dB-SNDR 2nd-Order Gain-Error-Shaping and NS Pipelined SAR ADC Based on a Quantization-Prediction-Unrolled Scheme. 174-175 - Zongnan Wang, Lu Jie, Zichen Kong, Mingtao Zhan, Yi Zhong
A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer. 176-177 - Yanbo Zhang, Junyan Hao, Shubin Liu, Zhangming Zhu, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
A Single-Channel 70dB-SNDR 100MHz-BW 4th-Order Noise-Shaping Pipeline SAR ADC with Residue Amplifier Error Shaping. 178-179 - Casey Hardy, Hieu Minh Pham
A Scalable Heterogeneous Integrated Two-Stage Vertical Power-Delivery Architecture for High-Performance Computing. 182-183 - Tingxu Hu
A 12V-to-1V Quad-Output Switched-Capacitor Buck Converter with Shared DC Capacitors Achieving 90.4% Peak Efficiency and 48mA/mm3 Power Density at 85% Efficiency. 184-185 - Suhwan Kim, Harish K. Krishnamurthy, Sergey Sofer, Sheldon Weng, Shahar Wolf, Ashoke Ravi, Krishnan Ravichandran, Ofir Degani, James W. Tschanz, Vivek De:
A 1.8W High-Frequency SIMO Converter Featuring Digital Sensor-Less Computational Zero-Current Operation and Non-Linear Duty-Boost. 186-187 - Wei-Chieh Hung, Cheng-Wen Chen, Yu-Wei Huang, An Chen, Zhen-Yu Yang, Ke-Horng Chen
A Double Step-Down Dual-Output Converter with Cross Regulation of 0.025mV/mA and Improved Current Balance. 188-189 - Casey Hardy, Hanh-Phuc Le
A 21W 94.8%-Efficient Reconfigurable Single-Inductor Multi-Stage Hybrid DC-DC Converter. 190-191 - Zhiguo Tong
A 42W Reconfigurable Bidirectional Power Delivery Voltage-Regulating Cable. 192-193 - Cheng Lin, Chieb-Sheng Hung, Si-Yi Li, Ya-Ting Hsu, Ke-Horng Chen
A Wide 0.1-to-10 Conversion-Ratio Symmetric Hybrid Buck-Boost Converter for USB PD Bidirectional Conversion. 194-195 - Xu Yang, Linhu Zhao, Menglian Zhao, Zhichao Tan, Yong Ding, Wuhua Li, Wanyuan Qu:
A 5A 94.5% Peak Efficiency 9~16V-to-1V Dual-Path Series-Capacitor Converter with Full Duty Range and Low V.A Metric. 196-197 - Guigang Cai, Yan Lu, Rui Paulo Martins:
A Compact 12V-to-1V 91.8% Peak Efficiency Hybrid Resonant Switched-Capacitor Parallel Inductor (ReSC-PL) Buck Converter. 198-199 - Wen-Liang Zeng, Guigang Cai, Chon-Fai Lee, Chi-Seng Lam, Yan Lu, Sai-Weng Sin, Rui Paulo Martins:
A 12V-lnput 1V-1.8V-Output 93.7% Peak Efficiency Dual-Inductor Quad-Path Hybrid DC-DC Converter. 200-201 - Mayank Raj, Chuan Xie, Ade Bekele, Adam Chou, Wenfeng Zhang, Ying Cao, Jae Wook Kim, Nakul Narang, Hongyuan Zhao, Yipeng Wang, Kee Hian Tan, Winson Lin, Jay Im, David Mahashin, Santiago Asuncion, Parag Upadhyaya, Yohan Frans:
A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies. 204-205 - Kadaba Lakshmikumar, Alexander Kurylak, Romesh Kumar Nandwana, Bibhu Das, Joe Pampanin, Mike Brubaker, Pavan Kumar Hanumolu:
A 7 pA/$\surd\text{Hz}$ Asymmetric Differential TIA for 100Gb/s PAM-4 links with -14dBm Optical Sensitivity in 16nm CMOS. 206-207 - Ahmed E. AbdelRahman
A Carrier-Phase-Recovery Loop for a 3.2pJ/b 24Gb/s QPSK Coherent Optical Receiver. 208-209 - Yuto Yakubo, Kazuma Furutani, Kouhei Toyotaka, Haruki Katagiri, Masashi Fujita, Munehiro Kozuma, Yoshinori Ando, Yoshiyuki Kurokawa, Toru Nakura, Shunpei Yamazaki:
Crystalline Oxide Semiconductor-based 3D Bank Memory System for Endpoint Artificial Intelligence with Multiple Neural Networks Facilitating Context Switching and Power Gating. 212-213 - Jinhai Lin
A 47nW Mixed-Signal Voice Activity Detector (VAD) Featuring a Non-Volatile Capacitor-ROM, a Short-Time CNN Feature Extractor and an RNN Classifier. 214-215 - Noriyuki Miura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Takaaki Okidono, Takuji Miki, Makoto Nagata:
A Triturated Sensing System. 216-217 - Kotaro Naruse, Takayuki Ueda, Jun Shiomi, Yoshihiro Midoh, Noriyuki Miura:
A Self-Programming PUF Harvesting the High-Energy Plasma During Fabrication. 218-219 - Craig Ives, Ali Hajimiri:
Subtractive Photonic Waveguide-Coupled Photodetectors in 180nm Bulk CMOS. 220-221 - Md Jubayer Shawon, Vishal Saxena
A Silicon Photonic Reconfigurable Optical Analog Processor (SiROAP) with a 4x4 Optical Mesh. 222-223 - Qiaochu Zhang
A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur. 226-227 - Yumeng Yang, Wei Deng, Angxiao Yan, Haikun Jia, Junlong Gong, Zhihua Wang, Baoyong Chi:
A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1st/2nd-Order DTC INL Calibration. 228-229 - Michael Zelikson, Kosta Luria, Lior Gil, Yuval Brown, Vadim Goldenbeg, Dor Kasif, Elias Hlees, Alex Vinichuk:
A Digital Low-Dropout (LDO) Linear Regulator with Adaptive Transfer Function Featuring 125A/mm2 Power Density and Autonomous Bypass Mode. 230-231 - Nicolas Butzen, Harish Krishnamurthy, Zakir Ahmed, Sheldon Weng, Krishnan Ravichandran, Michael Zelikson, James W. Tschanz, Jonathan Douglas:
A Monolithic 26A/mm2Imax, 88.5% Peak-Efficiency Continuously Scalable Conversion-Ratio Switched-Capacitor DC-DC Converter. 232-233 - Xinjian Liu, Daniel S. Truesdell, Omar Faruqe, Lalitha Parameswaran, Michael Rickley, Andrew Kopanski, Lauren Cantley, Austin Coon, Matthew Bernasconi, Tairan Wang
A Self-Powered SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for System-in-Fiber. 236-237 - Christopher J. Lukas
A 2.19µW Self-Powered SoC with Integrated Multimodal Energy Harvesting, Dual-Channel up to -92dBm WRX and Energy-Aware Subsystem. 238-239 - Kenichi Shimada, Keiichiro Sano, Kazuki Fukuoka, Hiroshi Morita, Masayuki Daito, Tatsuya Kamei, Hiroyuki Hamasaki, Yasuhisa Shimazaki:
A 33kDMIPS 6.4W Vehicle Communication Gateway Processor Achieving 10Gbps/W Network Routing, 40ms CAN Bus Start-Up and 1.4mW Standby Power. 240-241 - Guiming Shi
A 28nm 68MOPS 0.18\mu\mathrm{J}/\text{Op}$ Paillier Homomorphic Encryption Processor with Bit-Serial Sparse Ciphertext Computing. 242-243 - Raghavan Kumar, Avinash Varna, Carlos Tokunaga
A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS. 244-245 - Fengbin Tu, Zihan Wu, Yiqi Wang, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin:
MuITCIM: A 28nm $2.24 \mu\mathrm{J}$/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers. 248-249 - Shiwei Liu, Peizhe Li, Jinshan Zhang, Yunzhengmao Wang
A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine. 250-251 - Jinshan Yue, Chaojie He, Zi Wang, Zhaori Cong, Yifan He, Mufeng Zhou, Wenyu Sun, Xueqing Li, Chunmeng Dou, Feng Zhang, Huazhong Yang, Yongpan Liu, Ming Liu:
A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture. 252-253 - Fengbin Tu, Yiqi Wang, Zihan Wu, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin:
TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration. 254-255 - Sangjin Kim, Zhiyong Li
DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching. 256-257 - Wei-Hsing Huang, Tai-Hao Wen, Je-Min Hung, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Hung-Hsi Hsu, Yu-Hsiang Chin, Yu-Chiao Chen, Chuna-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W. 258-259 - Giuseppe Desoli, Nitin Chawla, Thomas Boesch, Manui Avodhyawasi, Harsh Rawat, Hitesh Chawla, VS Abhijith, Paolo Zambotti, Akhilesh Sharma, Carmine Cappetta, Michele Rossi, Antonio De Vita, Francesca Girardi:
A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications. 260-261 - Hongzhi Zhao
A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input. 264-265 - Serdar A. Yonar, Pier Andrea Francese
An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with $2\times$ Interpolating Sense-Amplifier-Latches. 266-267 - Wei-Hsin Tseng, Willy Lin, Chung-Wei Hsu, Chang-Yang Huang, Yu-Sian Lin, Hung-Yi Huang, HsinWei Chen, Sheng-Hui Liao, Kuan-Dar Chen, Jon Strange, Gabriele Manganaro:
A 14b 16GS/s Time-Interleaving Oirect-RF Synthesis OAe with T-OEM Achieving -70dBc IM3 up to 7.8GHz in 7nm. 268-269 - Sandeep Santhosh Kumar, Masahiro Kudo, Vlad Cretu, Antoine Morineau, Atsushi Matsuda, Minori Yoshida, Masazumi Marutani, Aadil Hussain Maniyar, Jay Kumar:
A 750mW 24GS/s 12b Time-Interleaved ADC for Direct RF Sampling in Modern Wireless Systems. 270-271 - Mingtao Zhan, Lu Jie, Nan Sun:
A 10mW 10-ENOB 1GS/s Ring-Amp-Based Pipelined TI-SAR ADC with Split MDAC and Switched Reference Decoupling Capacitor. 272-273 - Yi-Hu Wang, Soon-Jyh Chang:
A 7b 4.5GS/s 4× Interleaved SAR ADC with Fully On-Chip Background Timing Skew Calibration. 274-275 - Jia-Ching Wang, Tai-Haur Kuo:
A 3mW 2.7GS/s 8b Subranging ADC with Multiple-Reference-Reference-Embedded Comparators. 276-277 - Oian Chen, Yuan Liang
A Single-Channel 10GS/s 8b>36.4d8 SNDR Time-Domain ADC Featuring Loop-Unrolled Asynchronous Successive Approximation in 28nm CMOS. 278-279 - Jingzhi Zhang, Ajay Singhvi, Sherif S. Ahmed, Amin Arbabian:
A W-Band Transceiver Array with 2.4GHz LO Synchronization Enabling Full Scalability for FMCW Radar. 282-283 - Abhishek Agrawal, Amy Whitcombe, Woorim Shin, Ritesh Bhat, Somnath Kundu, Peter Sagazio, Hariprasad Chandrakumar, Thomas William Brown, Brent R. Carlton, Christopher D. Hull, Steven Callender, Stefano Pellerano:
A 128Gb/s 1.95pJ/b D-Band Receiver with Integrated PLL and ADC in 22nm FinFET. 284-285 - Bingzheng Yang, Zhixian Deng, Huizhen Jenny Qian, Xun Luo:
71-to-89GHz 12Gb/s Double-Edge-Triggered Quadrature RFDAC with LO Leakage Suppression Achieving 20.5dBm Peak Output Power and 20.4% System Efficiency. 286-287 - Ariane De Vroede, Patrick Reynaert:
A $4\times 4$ 607GHz Harmonic Injection-Locked Receiver Array Achieving $4.4\text{pW}/\surd\text{Hz}$ NEP in 28nm CMOS. 288-289 - Mohammad Ali Montazerolghaem, Leo C. N. de Vreede, Masoud Babaie:
A 300MHz-BW, 27-to-38dBm In-Band OIP3 sub-7GHz Receiver for 5G Local Area Base Station Applications. 292-293 - Soroush Araei
An Interferer-Tolerant Harmonic-Resilient Receiver with >+10dBm 3rd-Harmonic Blocker P1dB for 5G NR Applications. 294-295 - Xi Fu
A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low-Earth-Orbit Small Satellite Constellation. 296-297 - Dongwon You, Xi Fu
A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler. 298-299 - Si-Yi Li, Wei-Chien Hung, Tz-Wun Wang
A High Common-Mode Transient Immunity GaN-on-SOI Gate Driver for High dV/dt SiC Power Switch. 302-303 - Lixiong Du, Dong Yan, Dongsheng Brian Ma:
A Condition-Adaptive △f3-EMI Control GaN Switching Regulator With Modulation Frequency Envelope Tracking For Full-Spectrum Automotive CISPR 25 Compliance. 304-305 - Shu-Yung Lin, Ssu-Yu Lin, Sheng-Hsi Hung, Tz-Wun Wang
A GaN Gate Driver with On-chip Adaptive On-time Controller and Negative Current Slope Detector. 306-307 - Tz-Wun Wang
Multiple-Phase Accelerated Current Control in Bidirectional Energy Transfer of Automotive High-Voltage and Low-Voltage Batteries. 308-309 - Fatemeh Aghimand, Chelsea Hu, Saransh Sharma
A 65nm CMOS Living-Cell Dynamic Fluorescence Sensor with 1.05fA Sensitivity at 600/700nm Wavelengths. 312-313 - Qiuyang Lin, Wim Sijbers, Christina Avdikou, Didac Gomez Salinas, Dwaipayan Biswas
A $\boldsymbol{22\mu \mathrm{W}}$ Peak Power Multimodal Electrochemical Sensor Interface IC for Bioreactor Monitoring. 314-315 - Dongwon Lee, Doohwan Jung, Fuze Jiang, Gregory Villiam Junek, Jongseok Park, Hangxing Liu, Ying Kong, Youngin Kim, Jing Wang
A CMOS Multi-Functional Biosensor Array for Rapid Low-Concentration Analyte Detection with On-Chip DEP-Assisted Active Enrichment and Manipulation with No External Electrodes. 316-317 - Anh Chu, Michal Kern
A 263GHz 32-Channel EPR-on-a-Chip Injection-Locked VCO-Array. 318-319 - Shihkai Kuo, Manideep Dunna, Hongyu Lu
An LTE-Harvesting BLE-to-WiFi Backscattering Chip for Single-Device RFID-Like Interrogation. 320-321 - Jong-Kyoung Lee, Sunsik Woo
ASIL-D Compliant Battery Monitoring IC with High Measurement Accuracy and Robust Communication. 322-323 - Francesco Conti, Davide Rossi, Gianna Paulin
A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing. 326-327 - Wenyu Sun, Xiaoyu Feng, Chen Tang, Shupei Fan, Yixiong Yang, Jinshan Yue, Huazhong Yang, Yongpan Liu:
A 28nm 2D/3D Unified Sparse Convolution Accelerator with Block-Wise Neighbor Searcher for Large-Scaled Voxel-Based Point Cloud Network. 328-329 - Seunghyun Moon
A 127.8TOPS/W Arbitrarily Quantized 1-to-8b Scalable-Precision Accelerator for General-Purpose Deep Learning with Reduction of Storage, Logic and Latency Waste. 330-331 - Cheng-Yan Du, Chieh-Fu Tsai, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang:
A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow. 332-333 - Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Donghyeon Han, Hoi-Jun Yoo:
C-DNN: A 24.5-85.8TOPS/W Complementary-Deep-Neural-Network Processor with Heterogeneous CNN/SNN Core Architecture and Forward-Gradient-Based Sparsity Generation. 334-335 - Jilin Zhang, Dexuan Huo, Jian Zhang, Chunqi Qian, Qi Liu, Liyang Pan, Zhihua Wang, Ning Qiao, Kea-Tiong Tang, Hong Chen:
ANP-I: A 28nm 1.5pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-O.1 μJ/Sample On-Chip Learning for Edge-AI Applications. 336-337 - Yuchuan Gong, Teng Zhang, Hongtao Guo, Xiyuan Liu, Jingxiao Zheng, Hongqiang Wu, Conghan Jia, Luying Que, Liang Zhou, Liang Chang, Jun Zhou:
DL-VOPU: An Energy-Efficient Domain-Specific Deep-Learning-Based Visual Object Processing Unit Supporting Multi-Scale Semantic Feature Extraction for Mobile Object Detection/Tracking Applications. 338-339 - Sungjin Park
A0.81 mm2 740μW Real-Time Speech Enhancement Processor Using Multiplier-Less PE Arrays for Hearing Aids in 28nm CMOS. 340-341 - Thierry Tambe
A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management. 342-343 - Jihang Gao, Linxiao Shen, Heyi Li, Siyuan Ye, Jie Li, Xinhang Xu, Jiajia Cui, Yunhung Gao, Ru Huang, Le Ye:
A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting. 346-347 - Zhong Tang, Nandor G. Toth
A 40A Shunt-Based Current Sensor with ±0.2% Gain Error from -40°C to 125°C and Self-Calibration. 348-349 - Amirhossein Jouvaeian, Qinwen Fan, Mario Motz, Udo Ausserlechner, Kofi A. A. Makinwa:
A 51A Hybrid Magnetic Current Sensor with a Dual Differential DC Servo Loop and 43mArms Resolution in a 5MHz Bandwidth. 350-351 - Kim Allinger, Matthias KuhI:
A Closed-Loop 12bit CMOS-Integrated Stress Sensor System with 4bit Adjustable Sensitivity from 178 to 11 kPa/LSB at up to 22.5kS/s and 5bit Dynamic Range Adjustment. 352-353 - Zhong Tang, Sining Pan, Kofi A. A. Makinwa:
A Sub-1V 810nW Capacitively-Biased BJT-Based Temperature Sensor with an Inaccuracy of ±0.15°C (3σ) from -55°C to 125°C. 354-355 - Yuting Shen, Hanyue Li, Eugenio Cantatore, Pieter Harpe:
A 2.98pJ/conversion 0.0023mm2 Dynamic Temperature Sensor with Fully On-Chip Corrections. 356-357 - Nandor G. Toth
A BJT-Based Temperature Sensor with $\pm 0.1^{\circ}\mathrm{C}(3\sigma)$ Inaccuracy from -55°C to 125°C and a 0.85pJ.K2 Resolution FoM Using Continuous-Time Readout. 358-359 - Liang Gao
A 0.64-to-0.69THz Beam-Steerable Coherent Source with 9.1dBm Radiated Power and 30.8dBm Lensless EIRP in 65nm CMOS. 362-363 - Byeong-Taek Moon
A 264-to-287GHz, -2.5dBm Output Power, and -92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fsrms Jitter D-Band Cascaded Sub-Sampling PLL. 364-365 - Shuyang Li, Xingcun Li
A 200-to-350GHz SiGe BiCMOS Frequency Doubler with Slotline-Based Mode-Decoupling Harmonic-Tuning Technique Achieving 1.1-to-4.7dBm Output Power. 366-367 - Jiaxiang Li, Yun Yin, Hang Chen, Jie Lin, Yicheng Li, Xianglong Jia, Zhen Hu, Xiuyin Zhang
A 4.1 W Quadrature Doherty Digital Power Amplifier with 33.6% Peak PAE in 28nm Bulk CMOS. 370-371 - Weisen Zeng, Li Gao, Ningzheng Sun
A 19.7-to-43.8GHz Power Amplifier with Broadband Linearization Technique in 28nm Bulk CMOS. 372-373 - Changxuan Han, Jie Zhou, Zhixian Deng, Yiyang Shu, Xun Luo:
A 4.8dB NF, 70-to-86GHz Deep-Noise-Canceling LNA Using Asymmetric Compensation Transformer and 4-to-1 Hybrid-Phase Combiner in 40nm CMOS. 374-375 - Soumya Krishnapuram Sireesh
A 4b RFDAC at 8GS/s for FMCW Chirps with 4GHz Bandwidth in $\boldsymbol{10\mu} \mathbf{s}$. 376-377 - Aravind Nagulu, Mingyu Yi, Yi Zhuang, Sasank Garikapati, Harish Krishnaswamy:
A 1-to-5GHz All-Passive Frequency-Translational 4th-Order N-path Filter with Low-Power Clock Boosting for High Linearity and Relaxed $\mathrm{P}_{\text{dc}}$-Frequency Trade-Off. 378-379 - Kyungho Ryu, Ji-Yong Jeong, Jung-Pil Lim, Kil-Hoon Lee, Kyongho Kim, Yongil Kwon, Seongjong Yoo, Siwoo Kim, Hyun-Wook Lim, Jae-Youl Lee:
A Source-Driver IC Including Power-Switching Fast-Slew-Rate Buffer and 8Gb/s Effective 3-Tap DFE Receiver Achieving 4.9mV DVRMS and 17V/ps Slew Rate for 8K Displays and Beyond. 382-383 - Seunghoon Ko, Junmin Lee, Juwon Ham, Byungcheol So, Daeyeol Cho, Hyeongjoon Kim, Bokman Kim, Woogeun Sim, Gyutae Youm:
Virtual Rotating Gesture Recognizable Touch Readout IC for 1.26" Circular Touch Screen Panel. 384-385 - San-Ho Byun, Heejin Lee, Tae-Gyun Song, Jinchul Lee, Jongmin Baek, Gyeongmin Ha, Seunghoon Baek, Yeongmin Kim, Won-Gab Jung, Hyun-Wook Lim, Siwoo Kim, Jae-Youl Lee:
A 45.8dB-SNR 120fps 100pF-Load Self-Capacitance Touch-Screen Controller with Enhanced In-Band Common Noise Immunity Using Noise Antenna Reference. 386-387 - John Rogers:
Some Recent Progress in Bioelectronics. 390 - Erik Winfree:
The Tall Thin Molecular Programmer. 392-393 - Devin Verreck, Piet Wambacq, Maarten Van De Put, Zubair Ahmed, Quentin Smets, Aryan Afzalian, Rutger Duflou, Xiangyu Wu, Gioele Mirabelli, Rongmei Chen, Inge Asselberghs, Gouri Sankar Kar:
The Promise of 2-D Materials for Scaled Digital and Analog Applications. 394-395 - Jelena Vuckovic, Geun Ho Ahn, Kasper Van Gasse, Melissa Guidry, Hyounghan Kwon, Jesse Lu, Daniil Lukin, Alexander Piggott, Neil V. Sapra, Logan Su, Jinhie Skarda, Rahul Trivedi, Dries Vercruysse, Alexander White, Joshua Yang, Ki Youl Yang:
Inverse Designed, Densely Integrated Classical and Quantum Photonics. 396-397 - Ali Khakifirooz, Eduardo Anaya, Sriram Balasubrahrmanyam, Geoff Bennett, Daniel Castro, John Egler, Kuangchan Fan, Rifat Ferdous, Kartik Ganapathi, Omar Guzman, Chang-Wan Ha, Rezaul Haque, Vinaya Harish, Majid Jalalifar, Owen Jungroth, Sung-Taeg Kang, Golnaz Karbasian, Jee-Yeon Kim, Siyue Li, Aliasgar S. Madraswala, Srivijay Maddukuri, Amr Mohammed, Shanmathi Mookiah, Shashi Nagabhushan, Binh Ngo, Deep Patel, Sai Kumar Poosarla, Naveen Prabhu V, Carlos Quiroga, Shantanu Rajwade, Ahsanur Rahman, Jalpa Shah, Rohit S. Shenoy, Ebenezer Tachie-Menson, Archana Tankasala, Sandeep Krishna Thirumala, Sagar Upadhyay, Krishnasree Upadhyayula, Ashley Velasco, Nanda Kishore Babu Vemula, Bhaskar Venkataramaiah, Jiantao Zhou, Bharat Pathak, Pranav Kalavade:
A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-NAND Technology and Featuring a 23.3Gb/mm2 Bit Density. 400-401 - Bvunarvul Kim, Seungpil Lee, Beomseok Hah, Kanawoo Park, Yongsoon Park, Kangwook Jo, Yujong Noh, Hyeon-Cheon Seol, Hyunsoo Lee, Jae-Hyeon Shin, Seongjin Choi, Youngdon Jung, Sungho Ahn, Yonghun Park, Sujeong Oh, Myungsu Kim, Seonauk Kim, Hyunwook Park, Taeho Lee, Haeun Won, Minsung Kim, Cheulhee Koo, Yeonjoo Choi, Suyoung Choi, Sechun Park, Dongkyu Youn, Junyoun Lim, Wonsun Park, Hwang Hur, Kichang Kwean, Hongsok Choi, Woopyo Jeong, Sungyong Chung, Jungdal Choi, Seonyong Cha:
A High-Performance 1Tb 3b/Cell 3D-NAND Flash with a 194MB/s Write Throughput on over 300 Layers $\mathsf{i}$. 402-403 - Jahoon Jin
A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization. 404-405 - Kwanyeob Chae, Jiyeon Park, Jaegeun Song, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Taekyung Yeo, Kyeongkeun Kang, Sangsoo Park, Eunsu Kim, Sukhyun Jung, Sanghune Park, Sungcheol Park, Mijung Noh, Hyo-Gyuem Rhew, Jongshin Shin:
A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection. 406-407 - Yuhwan Shin, Yongwoo Jo
A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces. 408-409 - Jung-Hun Park, Hyeonseok Lee, Hoyeon Cho, Sanghee Lee, Kwang-Hoon Lee, Han-Gon Ko, Deog-Kyoon Jeong:
A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS. 410-411 - Daehyun Kwon, Heon Su Jeong, Jaemin Choi, Wijong Kim, Jae Woong Kim, Junsub Yoon, Jungmin Choi, Sanguk Lee, Hyunsub Norbert Rie, Jin-Il Lee, Jongbum Lee, Taeseong Jang, JunHyung Kim, Sanghee Kang, Jung-Bum Shin, Yanggyoon Loh, Chang-Yong Lee, Junmyung Woo, Hye-Seung Yu, Changhyun Bae, Reum Oh, Young-Soo Sohn, Changsik Yoo, Jooyoung Lee:
A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL. 412-413 - Woongrae Kim, Chulmoon Jung, Seong Nyuh Yoo, Duckhwa Hong, Jeongjin Hwang, Jungmin Yoon, Oh-Yong Jung, Joonwoo Choi, Sanga Hyun, Mankeun Kang, Sangho Lee, Dohong Kim, Sanghyun Ku, Donhyun Choi, Nogeun Joo, Sangwoo Yoon, Junseok Noh, Byeongyong Go, Cheolhoe Kim, Sunil Hwang, Mihyun Hwang, Seol-Min Yi, Hyungmin Kim, Sanghyuk Heo, Yeonsu Jang, Kyoungchul Jang, Shinho Chu, Yoonna Oh, Kwidong Kim, Junghyun Kim, Soohwan Kim, Jeongtae Hwang, Sangil Park, Junphyo Lee, In-Chul Jeong, Joohwan Cho, Jonghwan Kim:
A 1.1V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement. 414-415 - Daehyun Kim, Nael Mizanur Rahman, Saibal Mukhopadhyay:
A 32.5mW Mixed-Signal Processing-in-Memory-Based k-SAT Solver in 65nm CMOS with 74.0% Solvability for 3D-Variable 126-Clause 3-SAT Problems. 418-419 - Shanshan Xie, Mengtian Yang, S. Andrew Lanham, Yipeng Wang, Meizhi Wang
Snap-SAT: A One-Shot Energy-Performance-Aware All-Digital Compute-in-Memory Solver for Large-Scale Hard Boolean Satisfiability Problems. 420-421 - Hyochan An, Yu Chen, Zichen Fan, Qirui Zhang
An 8.09TOPS/W Neural Engine Leveraging Bit-Sparsified Sign-Magnitude Multiplications and Dual Adder Trees. 422-423 - Stephen Felix, Shannon Morton, Simon Stacey, John Walsh:
Wafer-Level Stacking of High-Density Capacitors to Enhance the Performance of a Large Multicore Processor for Machine Learning Applications. 424-425 - Muya Chang, Ashwin Sanjay Lele, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat
A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking. 426-427 - Ji-Hwan SeoI, Heejin Yang
A $1.5\mu\mathrm{W}$ End-to-End Keyword Spotting SoC with Content-Adaptive Frame Sub-Sampling and Fast-Settling Analog Frontend. 428-429 - Jieyu Li
CCSA: A 394TOPS/W Mixed-Signal GPS Accelerator with Charge-Based Correlation Computing for Signal Acquisition. 430-431 - Arslan Riaz, Alperen Yasar, Furkan Ercan, Wei An, Jonathan Ngo, Kevin Galligan, Muriel Médard, Ken R. Duffy
A Sub-0.8pJ/b 16.3Gbps/mm2 Universal Soft-Detection Decoder Using ORBGRAND in 40nm CMOS. 432-433 - Sepideh Nouri, Subramanian S. Iyer:
An 8T eNVSRAM Macro in 22nm FDSOI Standard Logic with Simultaneous Full-Array Data Restore for Secure IoT Devices. 434-435 - Yeon-Woo Jeong, Seung-Ju Lee, Jong-Hun Kim, Mun-Jung Cho, Hwa-Soo Kim, Se-Un Shin:
30.1 A Scalable N-Step Equal Split SSHI Piezoelectric Energy Harvesting Circuit Achieving 1170% Power Extraction Improvement and 22nA Quiescent Current with a $\mathbf{1\mu{H}-{to}-10\mu H}$ Low Q Inductor. 438-439 - Zhen-Yu Yang, An Chen, Cheng-Wen Chen, Wei-Chieh Hung, Ke-Horng Chen
A 93.2%-Efficiency Multi-Input Bipolar Energy Harvester with $17.9\times$ MPPT Loss Reduction. 440-441 - Xinling Yue, Sundeep Javvaji, Zhong Tang, Kofi A. A. Makinwa, Sijun Du
A Bias-Flip Rectifier with a Duty-Cycle-Based MPPT Algorithm for Piezoelectric Energy Harvesting with 98% Peak MPPT Efficiency and 738% Energy-Extraction Enhancement. 442-443 - Yanqiao Li, Bahlakoana Mabetha
A 3. 7V-to-1kV Chip-Cascaded Switched-Capacitor Converter with Auxiliary Boost Achieving > 96{\%}$ Reactive Power Efficiency for Electrostatic Drive Applications. 444-445 - Seung-Ju Lee, Yean-Woo Jeong, Mun-Jung Cho, Jong-Hun Kim, Hwa-Soo Kim, Jun-Suk Bang, Se-Un Shin:
A 95.3% 5V-to-32V Wide Range 3-Level Current Mode Boost Converter with Fully State-based Phase Selection Achieving Simultaneous High-Speed $\mathbf{V}_{\text{CF}}$ Balancing and Smooth Transition. 446-447 - Ji Jin, Yufa Zhou, Changjin Chen, Xu Han, Weiwei Xu, Lin Cheng:
A 98.6%-Peak-Efficiency 1.47A/mm2-Current-Density Buck-Boost Converter with Always Reduced Conduction Loss. 448-449 - Yuanfei Wang, Mo Huang, Yan Lu, Rui Paulo Martins:
A Continuously Scalable-Conversion-Ratio SC Converter with Reconfigurable VCF Step for High Efficiency over an Extended VCR Range. 450-451 - Fei Huang, Hsing-Yen Tsai, Chi-Yu Huang, Yu-Chun Luo, Ching-Ho Li, Shao-Chang Huang, Yi-Hsiang Kao, Ke-Horng Chen
3D Wireless Power Transfer with Noise Cancellation Technique for -62dB Noise Suppression and 90.1% Efficiency. 452-453 - Ziyang Luo, Jin Liu, Hoi Lee:
A 90%-Efficiency 40.68MHz Single-Stage Dual-Output Regulating Rectifier with ZVS and Synchronous PFM Control for Wireless Powering. 454-455 - Filippo Neri, Gus Mehas, Fabio Di Fazio, Giovanni Figliozzi, Jure Menart, Marcin K. Augustyniak, Turev Acar, Amit Bavisi:
Single-Chip Qi-Compliant 40W Wireless-Power-Transmission Controller using RMS Coil Current Sensing and Adaptive ZVS for 4dB EMI and up to 1.7% Efficiency Improvements. 456-457 - Bowen Wang
A Quadrature Uncertain-IF IR-UWB Transceiver with Twin-OOK Modulation. 460-461 - Wan Kim
A Fully Integrated IEEE 802.15.4/4z-Compliant 6.5-to-8GHz UWB System-on-Chip RF Transceiver Supporting Precision Positioning in a CMOS 28nm Process. 462-463 - Jiaxin Lei, Xiliang Liu, Wei Song, Heng Huang, Xiaoyan Ma, Junliang Wei, Milin Zhang:
A 1.8Gb/s, 2.3pJ/bit, Crystal-Less IR-UWB Transmitter for Neural Implants. 464-465 - Changgui Yang, Zhihuan Zhang, Lei Zhang, Yunshan Zhang, Zhuhao Li, Yuxuan Luo, Gang Pan, Bo Zhao:
A 128-Channel 2mmx2mm Battery-Free Neural Dielet Merging Simultaneous Multi-Channel Transmission Through Multi-Carrier Orthogonal Backscatter. 466-467 - Ziyi Chang, Qijing Xiao
A Passive Bidirectional BLETag Demonstrating Battery-Free Communication in Tablet/Smartphone-to-Tag, Tag-to-Tablet/Smartphone, and Tag-to-Tag Modes. 468-469 - Zhizhan Yang
A ULP Long-Range Active-RF Tag with Automatic Antenna-Interface Calibration Achieving 20.5% TX Efficiency at -22dBm EIRP, and -60.4dBm Sensitivity at 17.8nW RX Power. 470-471 - Chunxiao Hu, Diyang Zheng, Yun Yin, Jie Lin, Yicheng Li, Wei Li, Hongtao Xu:
A 0.7-to-2.5GHz Sliding Digital-IF Quadrature Digital Transmitter Achieving >40% System Efficiency for Multi-Mode NB-IoT/BLE Applications. 472-473 - Hayden Bialek, Matthew L. Johnston, Arun Natarajan:
A 0.4-to-0.95GHz Distributed N-Path Noise-Cancelling Ultra-Low-Power RX with Integrated Passives Achieving -85dBm/100kb/s Sensitivity, -41dB SIR and 174dB RX FoM in 22nm CMOS. 474-475 - Hyunjoong Kim, Myeongwoo Kim, Kwangmuk Lee, Sanghyeon Cho, Chan Sam Park, Solwoong Song, Dae Sik Keum, Dong Pyo Jang, Jae Joon Kim:
A Behind-The-Ear Patch-Type Mental Healthcare Integrated Interface with 275-Fold Input Impedance Boosting and Adaptive Multimodal Compensation Capabilities. 478-479 - Kyeongho Eom, Minju Park, Han-Sol Lee, Seung-Beom Ku, Namju Kim, Seongkwang Cha
A Stimulus-Scattering-Free Pixel-Sharing Sub-Retinal Prosthesis SoC with 35.8dB Dynamic Range Time-Based Photodiode Sensing and Per-Pixel Dynamic Voltage Scaling. 480-481 - Taeryoung Seol
A 1V 136.6dB-DR 4kHz-BW $\Delta\Sigma$ Current-to-Digital Converter with a Truncation-Noise-Shaped Baseline-Servo-Loop in 0.18\mu\mathrm{m}$ CMOS. 482-483 - Geunha Kim, Sehwan Lee, Taeryoung Seol
A 1V-Supply $1.85\mathrm{V}_{\text{PP}}$ -Input-Range 1kHz-BW 181.9dB-FOMDR179.4dB-FOMSNDR 2nd-Order Noise-Shaping SAR-ADC with Enhanced Input Impedance in 0.18μm CMOS. 484-485 - Yingping Chen, Bernardo Tacca, Yunzhu Chen, Dwaipayan Biswas
A 384-Channel Online-Spike-Sorting IC Using Unsupervised Geo-OSort Clustering and Achieving 0.0013mm2/Ch and $1.78\mu \text{W/ch}$. 486-487 - Chne-Wuen Tsai, Rucheng Jiang, Lian Zhang, Miaolin Zhang, Liuhao Wu, Jiaqi Guo, Zhongwei Yan, Jerald Yoo:
SciCNN: A 0-Shot-Retraining Patient-Independent Epilepsy-Tracking SoC. 488-489 - Jianxiong Xu, José B. Sales Filho
Fascicle-Selective Bidirectional Peripheral Nerve Interface IC with 173dB FOM Noise-Shaping SAR ADCs and 1.38pJ/b Frequency-Multiplying Current-Ripple Radio Transmitter. 490-491 - Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Hon-Jarn Lin, Yen-An Chang, Cheng-Han Lu, Yu-Lin Chen, Chieh-Pu Lo, Chung-Chieh Chen, Cheng-Hsiung Kuo, Tan-Li Chou, Chia-Yu Wang, J. J. Wu, Roger Wang, Harry Chuang, Yih Wang
A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity. 494-495 - Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, De-Qi You, Fang-Yi Chen, Andrew Lee, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A 22nm 8Mb STT-MRAM Near-Memory-Computing Macro with 8b-Precision and 46.4-160.1TOPS/W for Edge-AI Devices. 496-497 - Jianguo Yang, Qing Luo, Xiaoyong Xue, Haijun Jiang, Qiqiao Wu, Zhongze Han, Yue Cao, Yongkang Han, Chunmeng Dou, Hangbing Lv, Qi Liu, Ming Liu:
A 9Mb HZO-Based Embedded FeRAM with 1012-Cycle Endurance and 5/7ns Read/Write using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier. 498-499 - Hao Cai, Zhong-Jian Bian, Yaoru Hou
A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference. 500-501 - Jinchen Wang, Mohamed I. Ibrahim
THz Cryo-CMOS Backscatter Transceiver: A Contactless 4 Kelvin-300 Kelvin Data Interface. 504-505 - Juhwan Yoo, Zijun Chen, Frank Arute, Shirin Montazeri, Marco Szalay, Catherine Erickson, Evan Jeffrey, Reza Fatemi, Marissa Giustina, Markus Ansmann
A 28-nm Bulk-CMOS IC for Full Control of a Superconducting Quantum Processor Unit-Cell. 506-507 - Yanshu Guo, Yaoyu Li, Wenqiang Huang, Songyao Tan, Qichun Liu, Tiefu Li, Ning Deng, Zhihua Wang, Yuanjin Zheng, Hanjun Jiang:
A Polar-Modulation-Based Cryogenic Qubit State Controller in 28nm Bulk CMOS. 508-509 - Kiseo Kang, Donggyu Minn, Jaeho Lee, Ho-Jin Song, Moonjoo Lee
A Cryogenic Controller IC for Superconducting Qubits with DRAG Pulse Generation by Direct Synthesis without Using Memory. 510-511 - Gengnanyang Zhang, Haichuan Lin, Cheng Wang:
A Calibration-Free 12.8-16.5GHz Cryogenic CMOS VCO with 202dBc/Hz FoM for Classic-Quantum Interface. 512-513
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