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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 43
Volume 43, Number 1, January 2024
- Hyunsu Chae
, Keren Zhu
ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design. 2-15 - Sadia Azam
Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review. 16-29 - Dmitrii Kirov
Efficient Encodings for Scalable Exploration of Cyber-Physical System Architectures. 30-43 - Wenhong Ma
Optimality-Guaranteed Design Space Pruning for CAN-FD Frame Packing. 44-56 - Vasudev Gohil
DETERRENT: Detecting Trojans Using Reinforcement Learning. 57-70 - Zhengfeng Huang
Design Guidelines and Feedback Structure of Ring Oscillator PUF for Performance Improvement. 71-84 - Tianyu Wang
A Bloom-Filter-Based Unique Address Checking Approach for DAG-Based Blockchain Systems. 85-98 - Wei Chen
Conflict-Free Parallel Data Access Technology for Matrix Calculation in Memory System of ASIP of 5G/6G Macro Base Stations. 99-112 - Wonyoung Lee
Highly VM-Scalable SSD in Cloud Storage Systems. 113-126 - Zhenge Jia
TinyML Design Contest for Life-Threatening Ventricular Arrhythmia Detection. 127-140 - Arman Roohi
PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel Accelerators. 141-150 - Shamiul Alam
Design Space Exploration for Phase Transition Material-Augmented MRAMs With Separate Read-Write Paths. 151-160 - Israel F. Araujo
Low-Rank Quantum State Preparation. 161-170 - Michael Vera-Panez
BeeGOns!: A Wireless Sensor Node for Fog Computing in Smart City Applications. 171-175 - Zihan Zhang
3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator. 176-188 - Jinyu Bai
CIMQ: A Hardware-Efficient Quantization Framework for Computing-In-Memory-Based Neural Network Accelerators. 189-202 - Sunan Zou
PowerSyn: A Logic Synthesis Framework With Early Power Optimization. 203-216 - Shamik Kundu
DiagNNose: Toward Error Localization in Deep Learning Hardware-Based on VTA-TVM Stack. 217-229 - Donglei Wu
FedComp: A Federated Learning Compression Framework for Resource-Constrained Edge Computing Devices. 230-243 - Daijoon Hyun
Accurate Interpolation of Library Timing Parameters Through Recurrent Convolutional Neural Network. 244-248 - Mengquan Li
Automated Optical Accelerator Search Toward Superior Acceleration Efficiency, Inference Robustness, and Development Speed. 249-262 - Wenjie Li
A Precision-Scalable Deep Neural Network Accelerator With Activation Sparsity Exploitation. 263-276 - Xing Huang
Control-Logic Synthesis of Fully Programmable Valve Array Using Reinforcement Learning. 277-290 - Ran Wei
Automated Model-Based Assurance Case Management Using Constrained Natural Language. 291-304 - Haihua Hu
Channel Parameter and Read Reference Voltages Estimation in 3-D NAND Flash Memory Using Unsupervised Learning Algorithms. 305-318 - Yao Tong
Analytical Modeling of Multiple Co-Existing Inaccuracies in RF Controlling Circuits for Superconducting Quantum Computing. 319-323 - Quan Nguyen-Gia
Modeling of Threshold Voltage Shift by Neighboring Transistors for Macaroni Channel MOSFETs in Series. 324-327 - Cong Wang
On Model Order Reduction and Exponential Integrator for Transient Circuit Simulation. 328-339 - Xiaoxiao Liang
RL-OPC: Mask Optimization With Deep Reinforcement Learning. 340-351 - Tiago Augusto Fontana
ILPGRC: ILP-Based Global Routing Optimization With Cell Movements. 352-365 - Husheng Han
Real-Time Robust Video Object Detection System Against Physical-World Adversarial Attacks. 366-379 - Yunpeng Song
Adaptive Differential Wearing for Read Performance Optimization on High-Density nand Flash Memory. 380-393 - Irith Pomeranz
Dynamic Test Compaction of a Compressed Test Set Shared Among Logic Blocks. 394-402
Volume 43, Number 2, February 2024
- Zheng Xiao
NGLIC: A Nonaligned-Row Legalization Approach for 3-D Interdie Connection. 404-416 - Tianchen Gu
BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis. 417-430 - Burin Amornpaisannon
Secure Run-Time Hardware Trojan Detection Using Lightweight Analytical Models. 431-441 - Janusz Rajski
H2B: Crypto Hash Functions Based on Hybrid Ring Generators. 442-455 - Kai-Xuan Lee, Chun-Chieh Lin, Tzu-Chiao Yen
FASE: Energy Isolation Framework for Latency-Sensitive Applications in Intermittent Systems With Multiple Peripherals. 456-467 - Yiwen Zhang, Hui Zheng
EDF-Based Energy-Efficient Semi-Clairvoyant Scheduling With Graceful Degradation. 468-479 - Yiwen Zhang, Jin-Peng Ma, Hui Zheng, Zonghua Gu
Criticality-Aware EDF Scheduling for Constrained-Deadline Imprecise Mixed-Criticality Systems. 480-491 - Zeming Cheng
A High-Performance, Conflict-Free Memory-Access Architecture for Modular Polynomial Multiplication. 492-505 - Chao Fang
Efficient N:M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design. 506-519 - Pei Yuan
Does Qubit Connectivity Impact Quantum Circuit Complexity? 520-533 - Weihong Liu
Ace-Sniper: Cloud-Edge Collaborative Scheduling Framework With DNN Inference Latency Modeling on Heterogeneous Devices. 534-547 - Jiandong Mu
Boosting the Convergence of Reinforcement Learning-Based Auto-Pruning Using Historical Data. 548-561 - Alireza Ghaffari
Statistical Hardware Design With Multimodel Active Learning. 562-572 - Amro Eldebiky
CorrectNet+: Dealing With HW Non-Idealities in In-Memory-Computing Platforms by Error Suppression and Compensation. 573-585 - Yang Bai
GTCO: Graph and Tensor Co-Design for Transformer-Based Image Recognition on Tensor Cores. 586-599 - Pavlos Zouridakis
Performance- and Energy-Aware Gait-Based User Authentication With Intermittent Computation for IoT Devices. 600-612 - Keyu Peng, Wenxing Zhu
Pplace-MS: Methodologically Faster Poisson's Equation-Based Mixed-Size Global Placement. 613-626 - Kyeonghyeon Baek
CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous Transistor Folding and Placement. 627-640 - Jing Mai
Multielectrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization. 641-653 - Rassul Bairamkulov
Power Aware Placement of On-Chip Voltage Regulators. 654-666 - Zhaoting Chen
pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment. 667-680 - Hongbing Tan
A Low-Cost Floating-Point Dot-Product-Dual-Accumulate Architecture for HPC-Enabled AI. 681-693 - Jerin Joe
Generation of Two-Cycle Tests for Structurally Similar Circuits. 694-703
Volume 43, Number 3, March 2024
- Sen Yin
Automatic Design for W-Band Front-End System via Bottom-Up Sizing and Layout Generation. 705-715 - Pruthvy Yellu, Nishanth Goud Chennagouni
INEAD: Intermediate Node Evaluation-Based Attack Detection for Secure Approximate Computing Systems. 716-727 - Ayesha Siddique, Khaza Anuarul Hoque
Moving Target Defense Through Approximation for Low-Power Neuromorphic Edge Intelligence. 728-741 - Minhui Zou
TDPP: 2-D Permutation-Based Protection of Memristive Deep Neural Networks. 742-755 - Lu Li
Compact Instruction Set Extensions for Kyber. 756-760 - Jiayun Zhou
ISA Extensions of Shuffling Against Side-Channel Attacks. 761-773 - Mohammad Ebrahimabadi
DELFINES: Detecting Laser Fault Injection Attacks via Digital Sensors. 774-787 - Jie Zou
Context-Aware Graceful Degradation for Mixed-Criticality Scheduling in Autonomous Systems. 788-801 - Rafaella Vale
Circuit Decomposition of Multicontrolled Special Unitary Single-Qubit Gates. 802-811 - Guanglong Li
HPPI: A High-Performance Photonic Interconnect Design for Chiplet-Based DNN Accelerators. 812-825 - Cheng-Yun Hsieh
Small Sampling Overhead Error Mitigation for Quantum Circuits. 826-839 - Jie Zhang
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets. 840-853 - Tuo Dai
Weave: Abstraction and Integration Flow for Accelerators of Generated Modules. 854-867 - Shuai Yang
Efficient Quantum Circuit Synthesis for SAT-Oracle With Limited Ancillary Qubit. 868-877 - Hongyan Li
Mortar-FP8: Morphing the Existing FP32 Infrastructure for High-Performance Deep Learning Acceleration. 878-891 - Jingyu Wang
ULSeq-TA: Ultra-Long Sequence Attention Fusion Transformer Accelerator Supporting Grouped Sparse Softmax and Dual-Path Sparse LayerNorm. 892-905 - Cenlin Duan
DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory. 906-918 - Chen Yang
Flexible and Efficient Convolutional Acceleration on Unified Hardware Using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D Winograd Units. 919-932 - Xiaoqiang Tang
Theoretical and Experimental Analysis of a CSWPL Behavioral Model for Microwave GaN Transistors Including DC Bias Voltages. 933-943 - Binwu Zhu
L2O-ILT: Learning to Optimize Inverse Lithography Techniques. 944-955 - Ziran Zhu
High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints. 956-969 - Chen-Chia Chang
Toward Fully Automated Machine Learning for Routability Estimator Development. 970-982 - Xiaoze Lin
Parallel Static Learning Toward Heterogeneous Computing Architectures. 983-993 - Yixuan Wang
POLAR-Express: Efficient and Precise Formal Reachability Analysis of Neural-Network Controlled Systems. 994-1007
Volume 43, Number 4, April 2024
- Sai Pentapati
Pin-3D: Effective Physical Design Methodology for Multidie Co-Optimization in Monolithic 3-D ICs. 1009-1022 - Hao Ding
Efficient 3-D Processor Array Reconfiguration Algorithms Based on Bucket Effect. 1023-1036 - Yu-Shun Hsiao
Silent Data Corruption in Robot Operating System: A Case for End-to-End System-Level Fault Analysis Using Autonomous UAVs. 1037-1050 - Xiaohui Wei
ApproxDup: Developing an Approximate Instruction Duplication Mechanism for Efficient SDC Detection in GPGPUs. 1051-1064 - Kaniz Mishty, Mehdi Sadi
System and Design Technology Co-Optimization of SOT-MRAM for High-Performance AI Accelerator Memory System. 1065-1078 - Luca Sterpone
CNN-Oriented Placement Algorithm for High-Performance Accelerators on Rad-Hard FPGAs. 1079-1092 - Hongyang Pan
Semi-Tensor Product-Based Exact Synthesis for Logic Rewriting. 1093-1106 - Jinming Zhang
INDM: Chiplet-Based Interconnect Network and Dataflow Mapping for DNN Accelerators. 1107-1120 - João Batista Pereira Matos Jr., Eddie B. de Lima Filho
Counterexample Guided Neural Network Quantization Refinement. 1121-1134 - Li Lu
Toward Critical Flip-Flop Identification for Soft-Error Tolerance With Graph Neural Networks. 1135-1148 - Chandramouli N. Amarnath
Error Resilience in Deep Neural Networks Using Neuron Gradient Statistics. 1149-1162 - Chen Yin
DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating. 1163-1176 - Liqiang Lu
Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition. 1177-1190 - Xiaoyu Sun
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros. 1191-1205 - Lihao Liu
GNN-Cap: Chip-Scale Interconnect Capacitance Extraction Using Graph Neural Network. 1206-1217 - Suhyeong Choi, Jinwook Jung
PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement. 1218-1231 - Ismail Bustany, Andrew B. Kahng
K-SpecPart: Supervised Embedding Algorithms and Cut Overlay for Improved Hypergraph Partitioning. 1232-1245 - Xinmiao Zhang
PDG: A Prefetcher for Dynamic Graph Updating. 1246-1259 - Hayoung Lee
A New Fail Address Memory Architecture for Cost-Effective ATE. 1260-1273 - Zahra Ramezani
On Input Generators for Cyber-Physical Systems Falsification. 1274-1287 - Hongfei Wang
GRAND: A Graph Neural Network Framework for Improved Diagnosis. 1288-1301 - Irith Pomeranz
Test Insertion for Dynamic Test Compaction. 1302-1306 - Jasmin Kaur, Alvaro Cintas Canto
Hardware Constructions for Error Detection in WG-29 Stream Cipher Benchmarked on FPGA. 1307-1311 - Binhao Bao
Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory. 1312-1316
Volume 43, Number 5, May 2024
- Long Zheng
PhGraph: A High-Performance ReRAM-Based Accelerator for Hypergraph Applications. 1318-1331 - Jiaye Li
Quantum KNN Classification With K Value Selection and Neighbor Selection. 1332-1345 - Ran Wei
DECISIVE: Designing Critical Systems With Iterative Automated Safety Analysis. 1346-1359 - Runze Wang
An Efficient GCNs Accelerator Using 3D-Stacked Processing-in-Memory Architectures. 1360-1373 - Vedika Saravanan
Noise Adaptive Quantum Circuit Mapping Using Reinforcement Learning and Graph Neural Network. 1374-1386 - Sven Thijssen
PATH: Evaluation of Boolean Logic Using Path-Based In-Memory Computing Systems. 1387-1400 - Dongdong Zhao
A Distributed and Parallel Accelerator Design for 3-D Acoustic Imaging on FPGA-Based Systems. 1401-1414 - Dewmini Sudara Marakkalage
Fanout-Bounded Logic Synthesis for Emerging Technologies. 1415-1428 - Xiangrong Xu
ATA-Cache: Contention Mitigation for GPU Shared L1 Cache With Aggregated Tag Array. 1429-1441 - Chao Xiao
Hierarchical Mapping of Large-Scale Spiking Convolutional Neural Networks Onto Resource-Constrained Neuromorphic Processor. 1442-1455 - Junpeng Wang
NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators With 3-D Stacked-DRAM. 1456-1469 - Liang Chang
General Purpose Deep Learning Accelerator Based on Bit Interleaving. 1470-1483 - Jingyu Pan
Lithography Hotspot Detection Based on Heterogeneous Federated Learning With Local Adaptation and Feature Selection. 1484-1496 - Lian Liu
An Automatic Neural Network Architecture-and-Quantization Joint Optimization Framework for Efficient Model Inference. 1497-1510 - Yufei Chen, Zizheng Guo
Dynamic Supply Noise Aware Timing Analysis With JIT Machine Learning Integration. 1511-1524 - Duo Wang
MoDSE: A High-Accurate Multiobjective Design Space Exploration Framework for CPU Microarchitectures. 1525-1537 - Soomin Kim
Enhancing Design Qualities Utilizing Multibit Flip-Flops: A Design and Technology Co-Optimization Driven Approach. 1538-1551 - Andrew B. Kahng
Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-Scale Complex IP Blocks. 1552-1565 - Fangzhou Wang
FastPass: A Fast Pin Access Analysis Framework for Detailed Routability Enhancement. 1566-1579 - Yu-Guang Chen
Aging-Aware Energy-Efficient Task Deployment of Heterogeneous Multicore Systems. 1580-1593 - Deheng Yang
Strider: Signal Value Transition-Guided Defect Repair for HDL Programming Assignments. 1594-1607 - Jie Yang
AEM-PCB Reverser: Circuit Schematic Generation in PCB Reverse Engineering Using Reinforcement Learning Based on Aesthetic Evaluation Metric. 1608-1612 - Jiajun Zhou, Jiajun Wu, Yizhao Gao, Yuhao Ding, Chaofan Tao, Boyu Li, Fengbin Tu, Kwang-Ting Cheng, Hayden Kwok-Hay So, Ngai Wong:
DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference. 1613-1617 - Longfei Luo
Revisiting TRIM on High-Density Flash-Based Hybrid Storage Systems. 1618-1622
Volume 43, Number 6, June 2024
- Peiyu Liao
Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration. 1624-1637 - Shixin Chen
Floorplet: Performance-Aware Floorplan Framework for Chiplet Integration. 1638-1649 - Yuqin Dou
FPAX: A Fast Prior Knowledge-Based Framework for DSE in Approximate Configurations. 1650-1662 - Shivam Aggarwal
Chameleon: Dual Memory Replay for Online Continual Learning on Edge Devices. 1663-1676 - Idris Somoye
Self-Assertion-Based Countermeasures Within a RISC-V Microprocessor for Coverage of Information Leakage Faults. 1677-1690 - Chunlin Song, Xianzhang Chen
Optimizing the Performance of Consistency-Aware Deduplication Using Persistent Memory. 1691-1703 - Mingze Ma
Efficient Pipelining of Synchronous Dataflow Graphs Via Graph Conversion. 1704-1714 - Zhiwei Feng
On the Scheduling of Fault-Tolerant Time-Sensitive Networking With IEEE 802.1CB. 1715-1728 - Tianshuo Bai
An End-to-End In-Memory Computing System Based on a 40-nm eFlash-Based IMC SoC: Circuits, Toolchains, and Systems Co-Design Framework. 1729-1740 - Huize Li
CPSAA: Accelerating Sparse Attention Using Crossbar-Based Processing-In-Memory Architecture. 1741-1754 - Weizhou Huang
TieredHM: Hotspot-Optimized Hash Indexing for Memory-Semantic SSD-Based Hybrid Memory. 1755-1768 - Tsun-Yu Yang, Xiangjun Peng, Wang Kang
Toward Write Optimization for Skyrmion Racetrack Memory by Skyrmion Repermutation. 1769-1780 - Mingkai Chen
An Energy-Efficient In-Memory Accelerator for Graph Construction and Updating. 1781-1793 - Qian Wei
A Semantic-Integrated LSM-Tree-Based Key-Value Storage Engine for Blockchain Systems. 1794-1807 - Eunji Kwon
Mobile Transformer Accelerator Exploiting Various Line Sparsity and Tile-Based Dynamic Quantization. 1808-1821 - Zheyu Yan
U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Accelerators. 1822-1833 - Zhiding Liang
NAPA: Intermediate-Level Variational Native-Pulse Ansatz for Variational Quantum Algorithms. 1834-1847 - Jing Cao
FedStar: Efficient Federated Learning on Heterogeneous Communication Networks. 1848-1861 - Jinfeng Ye
Fast Aging-Aware Timing Analysis Framework With Temporal-Spatial Graph Neural Network. 1862-1871 - Lixin Liu
Xplace: An Extremely Fast and Extensible Placement Framework. 1872-1885 - Haodong Lin
Fast Online Reconstruction for SSD-Based RAID-5 Storage Systems. 1886-1899 - Chenghong Zhang
Blade-DA: Click-Based Asynchronous Resilient Circuit With Dynamic Delay Adjustment. 1900-1913 - Yongchao Wang
EBDN: Entropy-Based Double Nonuniform Sensing Algorithm for LDPC Decoding in TLC nand Flash Memory. 1914-1918 - Jianchi Sun
Efficient Data Extraction Circuit for Posit Number System: LDD-Based Posit Decoder. 1919-1923 - Mohammed Nabeel
Silicon-Proven ASIC Design for the Polynomial Operations of Fully Homomorphic Encryption. 1924-1928
Volume 43, Number 7, July 2024
- Shujie Pang
Minato: A Read-Disturb-Aware Dynamic Buffer Management Scheme for NAND Flash Memory. 1930-1943 - Suwan Kim, Heechun Park
Comprehensive Physical Design Flow Incorporating 3-D Connections for Monolithic 3-D ICs. 1944-1956 - Nesara Eranna Bethur
Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs. 1957-1970 - Zhenyu Guan
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation. 1971-1983 - Fu Yao
Optimizing AES Threshold Implementation Under the Glitch-Extended Probing Model. 1984-1997 - Zhixin Pan
TD-Zero: Automatic Golden-Free Hardware Trojan Detection Using Zero-Shot Learning. 1998-2011 - Renping Liu
Fair-ZNS: Enhancing Fairness in ZNS SSDs Through Self-Balancing I/O Scheduling. 2012-2022 - Nan Che, Weihua Chen
OS-Level PMC-Based Runtime Thermal Control for ARM Mobile CPUs. 2023-2036 - Chao Lu
QuBEC: Boosting Equivalence Checking for Quantum Circuits With QEC Embedding. 2037-2042 - Lixia Han
CoMN: Algorithm-Hardware Co-Design Platform for Nonvolatile Memory-Based Convolutional Neural Network Accelerators. 2043-2056 - Ankit Wagle, Gian Singh
An ASIC Accelerator for QNN With Variable Precision and Tunable Energy Efficiency. 2057-2070 - Aojie Jiang
GroupQ: Group-Wise Quantization With Multi-Objective Optimization for CNN Accelerators. 2071-2083 - Sifan Sun
CIM²PQ: An Arraywise and Hardware-Friendly Mixed Precision Quantization Method for Analog Computing-In-Memory. 2084-2097 - Jiechen Huang
The Floating Random Walk Method With Symmetric Multiple-Shooting Walks for Capacitance Extraction. 2098-2111 - Wenjie Zhong
A Verification Framework for Time-Triggered Networks Based on Timed Colored Petri Net. 2112-2125 - Ciyan Zheng
The First Implementation of a Memtranstor Emulator and its Artificial Synaptic Plasticity Analysis. 2126-2139 - Guojin Chen
Ultrafast Source Mask Optimization via Conditional Discrete Diffusion. 2140-2150 - Wei W. Xing
Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICs. 2151-2162 - Yen-Wen Chen, Rui-Hsuan Wang, Yu-Hsiang Cheng, Chih-Cheng Lu
SUN: Dynamic Hybrid-Precision SRAM-Based CIM Accelerator With High Macro Utilization Using Structured Pruning Mixed-Precision Networks. 2163-2176 - Gen Zhang
Instiller: Toward Efficient and Realistic RTL Fuzzing. 2177-2190 - Md Rubel Ahmed
AutoModel: Automatic Synthesis of Models From Communication Traces of SoC Designs. 2191-2204 - Aibin Yan
MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method. 2205-2214 - Hongyu Fan
Leveraging Datapath Propagation in IC3 for Hardware Model Checking. 2215-2228 - Lorenzo Lagostina
Mix & Latch: Comparison With State-of-the-Art Retiming on a RISC-V Benchmark. 2229-2233
Volume 43, Number 8, August 2024
- Changle Zhi
Multiobjective Optimization for PSIJ Mitigation and Impedance Improvement Based on PCPS/DR-NSDE in Chiplet-Based 2.5-D Systems. 2235-2248 - Ramesh Sambangi
Congestion-Aware Vertical Link Placement and Application Mapping Onto 3-D Network-on-Chip Architectures. 2249-2262 - Shailja Pandey
3D-TemPo: Optimizing 3-D DRAM Performance Under Temperature and Power Constraints. 2263-2276 - Yibo Liu
Fast and Scaled Counting-Based Stochastic Computing Divider Design. 2277-2287 - Sathwika Bavikadi
ReApprox-PIM: Reconfigurable Approximate Lookup-Table (LUT)-Based Processing-in-Memory (PIM) Machine Learning Accelerator. 2288-2300 - Eric Hunt-Schroeder
Tamper Resistant Reconfigurable Preamplifier Physical Unclonable Function With Self-Destruct. 2301-2311 - Ruiqi Lu
Secure and Low-Delay CAN-FD Communication in Embedded Microcontroller: A Cooperative Swapping Approach. 2312-2325 - Yogendra Sao
DefScan: Provably Defeating Scan Attack on AES-Like Ciphers. 2326-2339 - Mohsen Shekarisaz
Inter-Task Energy-Hotspot Elimination in Fixed-Priority Real-Time Embedded Systems. 2340-2353 - Xi Deng
A Low-Power Variation-Tolerant 7T SRAM With Enhanced Read Sensing Margin for Voltage Scaling. 2354-2364 - Ardhendu Sarkar, Surajeet Ghosh
Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment. 2365-2378 - Yichuan Bai
A Compilation Framework for SRAM Computing-in-Memory Systems With Optimized Weight Mapping and Error Correction. 2379-2392 - Fan Zhang
On-Device Continual Learning With STT-Assisted-SOT MRAM-Based In-Memory Computing. 2393-2404 - Yueting Li
APIM: An Antiferromagnetic MRAM-Based Processing-In-Memory System for Efficient Bit-Level Operations of Quantized Convolutional Neural Networks. 2405-2410 - Ching-Yuan Chen
Mitigating Slow-to-Write Errors in Memristor-Mapped Graph Neural Networks Induced by Adversarial Attacks. 2411-2425 - Lixin Liu
Parmesan: Efficient Partitioning and Mapping Flow for DNN Training on General Device Topology. 2426-2439 - Zhiming Fan, Jiajun Huang, Jialin Cai
Design of Sequential Load Modulation Balance Amplifier Using Multiobjective Particle Swarm Algorithm. 2440-2451 - Zheyu Yan
Compute-in-Memory-Based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protections. 2452-2464 - Katherine Shu-Min Li, Fang-Chi Wu
Reinforcement Learning Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips. 2465-2478 - Zhanhui Shi
ARA-RCIV: Identifying Reliability-Critical Input Vectors of Logic Circuits Based on the Association Rules Analysis Approach. 2479-2492 - Jaehoon Ahn
DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement. 2493-2506 - Rémi Dekimpe
Cross-Domain Optimization of Low-Power Mixed-Signal Sensor Systems Under Classification Accuracy Constraints. 2507-2517 - Seung Ho Shin
GRAP: Efficient GPU-Based Redundancy Analysis Using Parallel Evaluation for Cross Faults. 2518-2531 - Zhuo Qian
Accelerating Real-Valued FFT on CPU-FPGA Platforms. 2532-2536
Volume 43, Number 9, September 2024
- Xuanliang Deng
Priority Assignment for Global Fixed Priority Scheduling on Multiprocessors. 2538-2550 - Lucas Deutschmann
A Scalable Formal Verification Methodology for Data-Oblivious Hardware. 2551-2564 - Chin-Hsien Wu
A Hash-Based Clustering System Software for Intermittent Computing Devices With NAND Flash Memory. 2565-2577 - Songran Liu
RTeX: An Efficient and Timing-Predictable Multithreaded Executor for ROS 2. 2578-2591 - Jaeyoung Kang
DRAM-Based Acceleration of Open Modification Search in Hyperdimensional Space. 2592-2605 - Youlin Pan, Genggeng Liu
NR-Router+: Enhanced Non-Regular Electrode Routing With Optimal Pin Selection for Electrowetting-on-Dielectric Chips. 2606-2619 - Yanqi Pan
Delaying Crash Consistency for Building A High-Performance Persistent Memory File System. 2620-2634 - Yintao He
A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks. 2635-2646 - Jindong Li
FireFly v2: Advancing Hardware Support for High-Performance Spiking Neural Network With a Spatiotemporal FPGA Accelerator. 2647-2660 - Sungju Ryu
Mobileware: Distributed Architecture With Channel Stationary Dataflow for MobileNet Acceleration. 2661-2673 - Wenqian Zhao
AdaOPC 2.0: Enhanced Adaptive Mask Optimization Framework for via Layers. 2674-2686 - Zhiqiang Liu
Randomized Cholesky Factorization With Threshold-Based Multisampling for Power Grid Simulation. 2687-2691 - Bing-Xin Liu
Complete Security Solution for Practical Quantum Network Coding. 2692-2704 - Meng Zhang, Zheng Zhang
Fast Constraints Tuning via Transfer Learning and Multiobjective Optimization. 2705-2718 - Menghao Long
Accurate Transmission and Crosstalk Estimation Methodology for Silicon Photonic WDM Filters. 2719-2729 - Zekun Zhu
A Fast SIE Solver With Cut Set Analysis and Terminals as Supernodes for Interconnects. 2730-2740 - Yen-Hsiang Huang
On Legalization of Die Bonding Bumps and Pads for 3-D ICs. 2741-2754 - Yuyang Ye
Timing-Driven Technology Mapping Approximation Based on Reinforcement Learning. 2755-2768 - Tingyuan Liang
AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA. 2769-2782 - Jieru Zhao
Hardware-Software Co-Design Enabling Static and Dynamic Sparse Attention Mechanisms. 2783-2796 - Jiajun Li
SPADIX: A Highly Efficient Accelerator for Solving 3-D Partial Differential Equations. 2797-2809 - Debjit Pal
ARISTOTLE: Feature Engineering for Scalable Application-Level Post-Silicon Debugging. 2810-2824 - Samit Shahnawaz Miftah
System-on-Chip Information Flow Validation Under Asynchronous Resets. 2825-2838
Volume 43, Number 10, October 2024
- Kevin Kai-Chun Chang, Guan-Ting Liu
Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems Perspective. 2840-2853 - Weidong Yang
RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture. 2854-2867 - Nikita Mirchandani
A High-Efficiency Power Obfuscation Switched-Capacitor DC-DC Converter Architecture. 2868-2873 - Zahra Ebrahimi
GREEN: An Approximate SIMD/MIMD CGRA for Energy-Efficient Processing at the Edge. 2874-2887 - Zhaokun Han
STATION: State Encoding-Based Attack-Resilient Sequential Obfuscation. 2888-2901 - Jingquan Ge
SnapMem: Hardware/Software Cooperative Memory Resistant to Cache-Related Attacks on ARM-FPGA Embedded SoC. 2902-2915 - Lu Zhang
RE-Specter: Examining the Architectural Features of Configurable CNN With Power Side-Channel. 2916-2929 - Jayeeta Chaudhuri
DAWN: Efficient Trojan Detection in Analog Circuits Using Circuit Watermarking and Neural Twins. 2930-2943 - Sangeet Saha
ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment. 2944-2957 - Ali Shiri Sichani
MCAM: Memductance Components Adaptive Model for Efficient Modeling of Memductance of Memristive Devices for Neuromorphic Circuits and Systems. 2958-2971 - Zhimin Zeng
Optimizing Secure Deletion in Interlaced Magnetic Recording With Move-on-Cover Approach. 2972-2977 - Ching-Yao Huang
Efficient Qubit Routing Using a Dynamically Extract-and-Route Framework. 2978-2989 - Baishakhi Rani Biswas
Systematic Generation of Memristor-Transistor Single-Phase Combinational Logic Cells. 2990-3003 - Yanghepu Li
A Parametric EDA Method for Coplanar Waveguide Channel Recognition and Air-Bridge Construction in Quantum Chip Design. 3004-3014 - Chao Lu
QHLS: An HLS Framework to Convert High-Level Descriptions to Quantum Circuits. 3015-3026 - Mengshu Sun
Hardware-Friendly 3-D CNN Acceleration With Balanced Kernel Group Sparsity. 3027-3040 - Wenqi Lou
Unleashing Network/Accelerator Co-Exploration Potential on FPGAs: A Deeper Joint Search. 3041-3054 - Jackson Melchert
Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays. 3055-3067 - Mridha Md Mashahedur Rahman
The Road Not Taken: eFPGA Accelerators Utilized for SoC Security Auditing. 3068-3082 - Gianpiero Cabodi
Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification. 3083-3087 - Xingbin Wang
EnsGuard: A Novel Acceleration Framework for Adversarial Ensemble Learning. 3088-3101 - Yidan Sun, Guiyuan Jiang
Layer Sequence Extraction of Optimized DNNs Using Side-Channel Information Leaks. 3102-3115 - Dmitry Utyamishev
Netwise Detection of Hardware Trojans Using Scalable Convolution of Graph Embedding Clouds. 3116-3128 - Qin Li
Secure Delegated Variational Quantum Algorithms. 3129-3142 - Yongan Zhang
AutoAI2C: An Automated Hardware Generator for DNN Acceleration on Both FPGA and ASIC. 3143-3156 - Zhenge Jia
Personalized Meta-Federated Learning for IoT-Enabled Health Monitoring. 3157-3170 - Jingwei Zhang
Intelligent Inverse Designs of Impedance Matching Circuits With Generative Adversarial Network. 3171-3183 - Haoyuan Wu
ChatEDA: A Large Language Model Powered Autonomous Agent for EDA. 3184-3197 - Lucas Klemmer
WAVING Goodbye to Manual Waveform Analysis in HDL Design With WAL. 3198-3211 - Benzheng Li, Shunyang Bi
MaPart: An Efficient Multi-FPGA System-Aware Hypergraph Partitioning Framework. 3212-3225 - Ying Zhang
On Modeling and Detecting Trojans in Instruction Sets. 3226-3239 - Ziwen Xiao
An MIV Test Method Using High-Precision Voltage Dividers. 3240-3249 - Soyed Tuhin Ahmed
One-Shot Online Testing of Deep Neural Networks Based on Distribution Shift Detection. 3250-3263 - Avinash Ayalasomayajula
Automatic Asset Identification for Assertion-Based SoC Security Verification. 3264-3277 - Aruna Jayasena
HIVE: Scalable Hardware-Firmware Co-Verification Using Scenario-Based Decomposition and Automated Hint Extraction. 3278-3291 - Taylor Barton
Multistage Charge Pump Design Methodology for Zero-Crossing-Based Amplifiers. 3292-3296
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