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12th ASICON 2017: Guiyang, China
- Yajie Qin, Zhiliang Hong, Ting-Ao Tang:
12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017. IEEE 2017, ISBN 978-1-5090-6625-4 - Franco Maloberti:
Keynote speech: Data converters for mobile and autonomous applications. XIV-XXI - Juin J. Liou:
Tutorial sessions: Electrostatic discharge protection of consumer electronics: Challenges and solutions. XXII-XXVI - Chun-Yen Chang, Chia-Chi Fan, Chien Liu, Yu-Chien Chiu, Chun-Hu Cheng:
High speed negative capacitance ferroelectric memory. 1-5 - TianShen Tang, Hao Ni, Zijian Zhao, Yao Zhou:
Development trends of embedded NVM technology. 6-11 - Amr M. S. Tosson, Shimeng Yu
, Mohab H. Anis, Lan Wei:
1T2R: A novel memory cell design to resolve single-event upset in RRAM arrays. 12-15 - Yun Yin, Junlin Gou, Junyi Wang, Yarong Fu, Xiaoyong Xue, Yinyin Lin:
ReRAM write circuit with dynamic uniform and small overshoot compliance current under PVT variations. 16-19 - Yun Li, Haihua Shen, Ce Li, Feng Zhang:
An efficient parity rearrangement coding scheme for RRAM thermal crosstalk effects. 20-23 - Akira Matsuzawa, Masaya Miyahara:
SAR+ΔΣ ADC with open-loop integrator using dynamic amplifier. 24-27 - Zhiyuan Dai, Hang Hu, Manxin Li, Fan Ye, Junyan Ren:
A 0.87 mW 7MHz-BW 76dB-SNDR passive noise-shaping modulator based on a SAR ADC. 28-31 - Xiaoqing Chen, Fan Ye, Junyan Ren:
A 13-bit non-binary weighted SAR ADC with bridge structure using digital calibration for capacitor weight error. 32-35 - Bao Li, Long Zhao, Yuhua Cheng:
Auxiliary testability design schemes for CMOS DACs with ultrahigh sampling rates. 36-39 - Yumei Ma, Mengfei Ji, Yuping Guo, Yuchun Chang:
A 101 dB SNDR 3.7mW switched-capacitor ΣΔ ADC using tri-level quantization. 40-43 - Yan Ye, Weili Han, Haiyue Yan, Fujiang Lin:
A highly linear voltage-to-time converter with variable conversion gain for time-based ADCs. 44-47 - Yongsheng Wang, Yang Liu, Xunzhi Zhou, Anyi Wang, Bei Cao, Fengchang Lai:
An on-chip signal conditioning delta-sigma ADC for micro-mechanical gyroscope applications. 48-51 - Saki Tajima, Nozomu Togawa
Soft error tolerant latch designs with low power consumption (invited paper). 52-55 - Runsheng Wang, Xiaobo Jiang, Shaofeng Guo, Ru Huang:
How close to the CMOS voltage scaling limit for FinFET technology? - Near-threshold computing and stochastic computing. 56-59 - Gang Li, Pengjun Wang, Yuejun Zhang:
A highly reliable lightweight PUF circuit with temperature and voltage compensated for secure chip identification. 60-63 - Daiki Asai, Masao Yanagisawa, Nozomu Togawa
Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems. 64-67 - Ya-Bei Fang, Pei-Yuan Chou, Bo-Hao Chen, Tay-Jyi Lin, Jinn-Shyan Wang:
An all-n-type dynamic adder for ultra-low-leakage IoT devices. 68-71 - Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
A new error masking flip-flop with one cycle correction penalty. 72-75 - Wei He, Hengyang Zhao, Zhongdong Qi, Hai-Bao Chen, Sheldon X.-D. Tan:
Fast two-dimensional finite element analysis for power network DC integrity checks of PCBs. 76-79 - En-Jui Chang
Overview of high-efficiency ant colony optimization (ACO)-based adaptive routings for traffic balancing in network-on-chip systems. 80-83 - Ye Huang, Xingquan Li
Cut redistribution and DSA template assignment for unidirectional design. 84-87 - Ludan Yang, Weiwei Pan, Zheng Shi, Yongjun Zheng:
A novel layout automation flow to facilitate test chip design for standard cell characterization. 88-91 - Jiangtao Peng, Hai-Bao Chen, Hengyang Zhao, Zeyu Sun, Sheldon X.-D. Tan:
Dynamic temperature-aware reliability modeling for multi-branch interconnect trees. 92-95 - Zhigang Li, Jinglei Huang, Qi Xu, Song Chen:
Integer linear programming based fault-tolerant topology synthesis for application-specific NoC. 96-99 - Patricia Desgreys, Venkata Narasimha Manyam
Wideband power amplifier predistortion: Trends, challenges and solutions. 100-103 - Haijun Shao, Dan Fan, Pan Xue, Hongguang Zhang, Yilei Shen, Yumei Huang, Gan Guo, Zhiliang Hong:
A LTE digital mixer with 25% duty quadrature 4-phase clocks. 104-107 - Zhao Wang, Dihu Chen, Jianping Guo:
A CMOS transceiver RFIC for China geo-radio standard. 108-111 - Jingxuan Chen, Wai Tung Ng
Design trends in smart gate driver ICs for power MOSFETs and IGBTs. 112-115 - Long Zhao, Feng Zou, Josh Yang, Tianshen Tang, Yuhua Cheng:
Analysis and characterization of process/layout impacts on the performance of high-speed analog circuits. 116-119 - Qinmiao Kang, Zhifeng Xie, Yongquan Liu, Ming Zhou:
A 0.18 μ m high-voltage area efficient integrated gate driver for piston engine fuel injection control SoC. 120-123 - Xin Liu, Yu Liu, Yanbin Xiao, Xiaohua Fan, Haiying Zhang:
An output-capacitor-less low-dropout regulator with transient-improved technique. 124-127 - Haobo Ruan, Tingyuan Yan, Yumei Huang:
A high-efficiency class e power amplifier with integrated finite DC feed inductance. 128-131 - Ruihan Pei, Jia Liu, Xian Tang, Fule Li, Zhihua Wang:
A low-offset dynamic comparator with input offset-cancellation. 132-135 - An Chen:
Cooptimization of emerging devices and architectures for energy-efficient computing. 136-139 - Chunmeng Dou, Wei-Hao Chen, Yi-Ju Chen, Huan-Ting Lin, Wei-Yu Lin, Mon-Shu Ho, Meng-Fan Chang:
Challenges of emerging memory and memristor based circuits: Nonvolatile logics, IoT security, deep learning and neuromorphic computing. 140-143 - Qingxi Duan, Teng Zhang, Minghui Yin, Caidie Cheng, Liying Xu, Yuchao Yang, Ru Huang:
Switching dynamics and computing applications of memristors: An overview. 144-147 - Qiang Chen, Chen Xin, Chenglong Zou
A low bit-width parameter representation method for hardware-oriented convolution neural networks. 148-151 - Sujuan Liu, Ning Lyu, ZiSheng Wang:
High-speed FPGA implementation of orthogonal matching pursuit for analog to information converter. 152-155 - Domenico Rossi:
Looking back and forward: The execution dilemma and the importance of innovation in the semiconductor industry. 156-159 - Xiaoxu Kang
Development and characterization of TaN thin film resistor with CMOS compatible fabrication process. 160-162 - Liang Zheng, Lin-Jie Yu, Lin Chen, Qing-Qing Sun, Wei Huang, Hao Zhu, David Wei Zhang:
Vertical power diodes based on bulk GaN substrates. 163-166 - Tailong Xu, Feng Xue, Zhikuang Cai, Xinning Liu, Shuo Meng:
A harmonic-free cell-based all-digital delay-locked loop for die-to-die clock synchronization of 3-D IC. 167-170 - Chengying Chen, Liming Chen, Xinghua Wang, Feng Zhang:
A 76μW, 58-dB SNDR analog front-end chip for implantable intraocular pressure detection. 171-174 - Wenhui Li, Awei Zhang, Weiwei Chen:
Design of a voltage-tunable pre-emphasis circuit utilizing a pseudo-differential cascode architecture. 175-178 - Hang Hu, Zhiyuan Dai, Manxin Li, Fan Ye, Junyan Ren:
A 320MS/s 7-b flash-SAR ADC with preamplifier sharing technique. 179-182 - Leiou Wang, Donghui Wang:
A gain factor controlled SUMPLE algorithm and system. 183-186 - Xu Yan
A 1.0-7.0 GHz inductorless RF mixer with multiple feedback and active load in 40-nm CMOS. 187-190 - Longmei Nan, Xiaoyang Zeng, Zhouchuang Wang, Yiran Du, Wei Li:
Research of a reconfigurable coarse-grained cryptographic processing unit based on different operation similar structure. 191-194 - Zheng-Yuan Su, Jun Wu, Yao Yao
A novel vertical semi-floating gate transistor for high-density ultrafast memory. 195-198 - Jiangtao Gu, Bo Wang, Chao Zhang, Tingbing Ouyang, Lizhao Gao:
A novel programmable pulse-broadening time amplifier controlled by node capacitance. 199-202 - Tian-Yu Wang, Lin-Jie Yu, Lin Chen, Hao Liu, Hao Zhu, Qing-Qing Sun, Shi-Jin Ding, Peng Zhou, David Wei Zhang:
Atomic layer deposited Hf0.5Zr0.5O2-based flexible RRAM. 203-206 - Zizhao Liu, Tao Pan, Song Jia, Uan Wang:
Design of a novel ternary SRAM sense amplifier using CNFET. 207-210 - Xiaoqiang Lv, Yimao Cai, Yuchao Yang, Zhizhen Yu, Yichen Fang, Zongwei Wang
A neural network circuit with associative learning and forgetting process based on memristor neuromorphic device. 211-214 - Ping Luo, Kangle Wang, Shuangjie Qiu, Zelang Liu, Long Huang:
A 40V monolithic ultrasonic motor driver. 215-218 - Zhongshan Zheng, Zhentao Li, Gengsheng Chen, Jiajun Luo, Zhengsheng Han:
Roles of the gate length and width of the transistors in increasing the single event upset resistance of SRAM cells. 219-221 - Liyi Xiao, Chunhua Qi, Tianqi Wang, Hongchen Li, Jiaqiang Li:
Low-cost resilient radiation hardened flip-flop design. 222-225 - Huizi Zhang, Chang Wu, Xiao Hu:
Heterogeneous computing for CNN. 226-229 - Jun Qiao, Xiao Wang, Yaohong Zhao:
Optimization of operational amplifier settling time by adjusting secondary poles based on gm/ID design. 230-232 - Zhen Zhu, Emma Salmi, Sauli Virtanen:
Residual stress study of thin films deposited by atomic layer deposition. 233-236 - Zhiwei Li, Yan Li, Song Chen, Feng Wu:
A fully pipelined hardware architecture for convolutional neural network with low memory usage and DRAM bandwidth. 237-240 - Hengzhou Yuan, Jianjun Chen, Bin Liang, Yang Guo:
A radiation hardened low-noise voltage-controlled-oscillator using negative feedback based multipath- current-releasing technology. 241-244 - Yimin Wu, Yongzhen Chen, Manxin Li, Fan Ye, Junyan Ren:
A stacked-packaged 16-channel ADC for ultrasound application. 245-248 - Haisheng Qian, Guangxi Hu, Laigui Hu
Analytical models for channel potential and drain current in AlGaN/GaN HEMT devices. 249-251 - Junhui Li, Liji Wu, Xiangmin Zhang:
An efficient HMAC processor based on the SHA-3 HASH function. 252-255 - Hansheng Wang, Minghui Zhang, Weiliang He, Lu Tang, Bin Jiang:
An improved equivalent circuit model for antenna: Modeling and parameter extraction. 256-258 - Xiang Ge, Hengliang Zhu, Fan Yang, Lingli Wang, Xuan Zeng:
Parallel sparse LU decomposition using FPGA with an efficient cache architecture. 259-262 - Xiaoqing Liu, Anping He, Caihong Li, Guangbo Feng, Jilin Zhang:
Study of 64-bit booth asynchronous multiplier based on FPGA. 263-266 - Liang Li, Ruizhi Sun, Ruoxi Wang, Fanjun Zang, Tao Jiang, Yang Li, Xinyang Wang, Yuchun Chang:
A 20MHz CTIA ROIC for InGaAs focal plane array. 267-270 - Mengting Li, Wenhao Sun, Zhimin Lu, Song Chen, Feng Wu:
Memristor-based material implication logic design for full adders. 271-274 - Xiudeng Wang, Xiaojing Zha, Yonggen Tu, Shi Ge, Yidie Ye, Yinshui Xia:
A synchronous charge extraction piezoelectric energy harvesting circuit based on precision active control peak detection with supplement energy. 275-278 - Min Liu, Ying Jian Yan, Wei Li:
Implementation and optimization of A5-1 algorithm on coarse-grained reconfigurable cryptographic logic array. 279-282 - Yewen Ni, Xiaoxin Cui, Tian Wang, Yuanning Fan, Qiankun Han, Kefei Liu, Xiaole Cui:
Improving DFA on AES using all-fault ciphertexts. 283-286 - Fan Feng, Li Li, Kun Wang, Feng Han, Hongbing Pan, Wei Li:
Application space exploration of a multi-fabric reconfigurable system. 287-290 - Jiaqi Yang, Jili Zhang, Xuefei Bai, Fujiang Lin:
A noise-shaping SAR ADC with dual error-feedback paths and alternate DACs. 291-294 - Yongzhen Chen, Yimin Wu, Fubiao Cao, Fan Ye, Junyan Ren:
A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs. 295-298 - Chunsheng Guo, Ju Meng, Zhiheng Liao
Influence of heat source size on thermal resistance of AlGaN/GaN HEMT. 299-302 - Fang-Fa Fu, Na Niu, Xiao-He Xian, Jinxiang Wang, Fengchang Lai:
An optimized topology reconfiguration bidirectional searching fault-tolerant algorithm for REmesh network-on-chip. 303-306 - Chenyang Kong, Xiaodong Liu, Weigang Xu, Zhangwen Tang:
A 1.0-to-2.4GHz wideband VCO with uniform sub-band interval and constant tuning gain. 307-310 - Jinghao Ye, Youhua Shi
A low cost and high speed CSD-based symmetric transpose block FIR implementation. 311-314 - Ying Zhang, Yujie Huang, Jun Han, Xiaoyang Zeng:
FPGA-based efficient implementation of SURF algorithm. 315-318 - Yujie Cai, Xin Li, Jun Han, Xiaoyang Zeng:
A configurable nonlinear operation unit for neural network accelerator. 319-322 - Chuanliang Kang, Pei Yang, Jian Wang, Jinmei Lai:
A deep research on the chip verification platform based on network. 323-326 - Jia-Wei Ma, Xuguang Guan, Tong Zhou, Tao Sun:
A new countermeasure against side channel attack for HMAC-SM3 hardware. 327-330 - Li Ding, Wenbo Yin:
A fully-pipelined hash table achieving low-latency and high throughput key-value retrieving system. 331-334 - Dongsheng Liu, Jiao Wang, Xiangcheng Sun, Jin Yan, Hi Lin:
A low input power charge pump for passive UHF RFID applications. 335-338 - Jia-wei Tan, Yang Guo, Jianjun Chen, Hengzhou Yuan, Xi Chen:
A state recovery design against single-event transient in high-speed phase interpolation clock and data recovery circuit. 339-342 - Lin-Jie Yu, Tian-Yu Wang, Lin Chen, Hao Zhu, Qing-Qing Sun, Shi-Jin Ding, Peng Zhou, David Wei Zhang:
Graphite planar resistive switching memory and its application in pattern recognition. 343-346 - Yanling Zhou, Yunyao Yan, Wei Yan:
A method to speed up VLSI hierarchical physical design in floorplanning. 347-350 - Xuejiao Ma, Yinshui Xia:
Power optimization based on dual-logic using And-Xor-Inverter Graph. 351-354 - Xin Ming, Xuan Zhang
PSR-enhanced low-dropout regulator using feedforward supply noise rejection technique. 355-358 - Rongsheng Zhang, Liyi Xiao, Jie Li:
A fast and accurate fault injection platform for SRAM-based FPGAs. 359-362 - Liyi Xiao, Anlong Li, Xuebing Cao, Hongchen Li, Rongsheng Zhang, Jie Li, Tianqi Wang:
A method to estimate cross-section of circuits at RTL levels. 363-366 - Yongsheng Wang, Xinzhi Li, Zhixin Zhang, Fengchang Lai:
A low gain error two-stage dB-linear variable gain amplifier in 0.35μm CMOS process. 367-370 - Hui Shen, Huiwen Yuan, Sitong Bu, Mingyue He, Daming Huang:
Low frequency noise characteristics in p-Type MOSFET with multilayer WSe2 channel and Al2O3 back gate dielectric. 371-374 - Yaopeng Kang, Pengjun Wang, Yuejun Zhang, Gang Li:
Design of ternary pulsed reversible counter based on CNFET. 375-378 - Mingbo Wang, Pengjun Wang, Qiang Fu, Huihong Zhang:
Delay and area optimization for FPRM circuits based on MSPSO algorithm. 379-382 - Baofa Huang, Ningyuan Yin, Zhiyi Yu:
The write deduplication mechanism based on a novel low-power data latched sense amplifier for a magnetic tunnel junction based non-volatile memory. 383-386 - Dongsheng Liu, Xiangcheng Sun, Jiao Wang, Fan Kang:
Implementation of an energy-efficient digital baseband controller compatible with EPC Class-1 Gen-2 standard. 387-390 - Yongsheng Wang, Shanshan Li, Ruoyang Wang, Xiaowei Liu:
LMS-FIR based digital background calibration for the four-channel time-interleaved ADC. 391-394 - Qichao He, Xiong Zhou, Qiang Li:
Optimization of the amplifier's input-referred noise for high resolution comparators. 395-397 - Yue Shi, Hongming Yu, Zekun Zhou:
A self-powered supply circuit for switching mode power supply. 398-401 - Jiaqi Gu, Ruoyao Wang, Jian Wang, Jinmei Lai, Qinghua Duan:
Remote embedded simulation system for SW/HW co-design based on dynamic partial reconfiguration. 402-405 - Xiaodong Liu, Chenyang Kong, Yifan Gao, Zhangwen Tang:
A 0.07-ppm/step differential digitally controlled crystal oscillator with guaranteed monotonicity. 406-409 - Yong Gu, Xuguang Guan, Tong Zhou:
The configurable current flattening circuit for DPA countermeasures. 410-413 - Wei Huang, Zhonghe Guo, Xiaohua Song, Fei Sun:
A cluster-scalable VLIW cryptography processor with high performance and energy efficiency. 414-417 - Toshiro Hiramoto, Tomoko Mizutani, Kiyoshi Takeuchi, Masaharu Kobayashi:
Parallel nonvolatile programming of power-up states of SRAM cells. 418-421 - You Yin:
Phase-change materials and memory devices for IoT application. 422-425 - Fujun Bai
A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area & 63% standby power. 426-428 - Jinghui Han, Yao Zhou, Hao Ni, Xiao Zheng, Yi Zhao:
A 55nm logic process compatible p-flash memory array fully demonstrated with high reliability. 429-432 - Kai-Ping Chang
Graphene nanodots with high-k dielectrics for flash memory applications. 433-435 - Jan Van der Spiegel, Milin Zhang, Xilin Liu
The next-generation brain machine interface system for neuroscience research and neuroprosthetics development. 436-439 - Yingdan Li, Fei Chen, Zhuoyi Sun, Zhaoyang Weng, Xian Tang, Hanjun Jiang, Zhihua Wang:
System architecture of a smart binaural hearing aid using a mobile computing platform. 440-443 - Chenjie Dong, Han Jin, IkHwan Kim, Chenyu Wang, Yajie Qin, Li-Rong Zheng:
An area efficient low power ECoG front-end chip for digitalized subdural grid. 444-447 - Yaxiong Lei, Xinpeng Xing, Haigang Feng, Zhihua Wang:
A 20Mbps 5.8mw QPSK transmitter based on injection locking and Class-E PA for wireless biomedical applications. 448-451 - Jinyong Zhang, Shing-Chow Chan, Hui Li, Lei Wang:
A 0.5 V 60 nW fully-differential log-domain band-pass filter with tunable cutoff frequency for biosensor applications. 452-455 - Lei Yang, Shaowei Zhen, Jiongwei Zheng, Shuiqing Xi, Xinjiang Gao, Zengxin Liu, He Tang, Ping Luo, Bo Zhang
A 110-dBΩ, 113-MHz variable-gain transimpedance amplifier for flash 3D imaging systems. 456-459 - Yaguang Li, Pingqiang Zhou:
An outlier detection method and its application to multicore-chip power estimation. 460-463 - Yingchieh Ho, Chen Hsu:
Energy-efficient standby current suppression with bootstrapped power-gating technique. 464-467 - Xiaorong Luo, Weiwei Ge, Bo Zhang
Ultralow power loss integratable high-voltage MOSFETs. 468-471 - Zheng Zhao, Zheng Wang
Optical computing on silicon-on-insulator-based photonic integrated circuits. 472-475 - Lining Zhang, Chenyue Ma, Mansun Chan:
A universal approach for signal dependent circuit reliability simulation. 476-479 - Jie Liu, M. P. Anantram, Xu Xu, Jiwu Lu:
Analysis of sub-threshold electron transport properties of ultra-scaled amorphous phase change material germanium telluride (invited paper). 480-483 - Yipeng Yuan, Zhihua Feng, Xuegong Zhou:
An on-line debug method for FPGAs. 484-487 - Liang Zhu, Yida Xie, Zhibo Ai:
DTCO through design space exploration by the virtual FAB range pattern matching flow. 488-491 - Xiaoxin Dou, Weiwei Pan, Zheng Shi, Yongjun Zheng:
Design and automatic generation of area-efficient ring oscillator based addressable test chips. 492-495 - Yu Zhou, Chun Shi, Zhengjie Deng, Alex Yakovlev:
Synthesis and optimization of asynchronous dual rail encoded circuits based on partial acknowledgement. 496-503 - Ting Ou, Deng Luo, Yuwei Zhang, Yiqiao Liao, Chang Cheng, Milin Zhang, Chun Zhang, Zhihua Wang, Xiang Xie:
Design of a closed-loop, bi-directional brain-machine-interface integrated on-chip spike sorting. 504-507 - Jie Zhou, Xi Chen, Tianzhun Wu, Guoxing Wang:
A fully differential high efficient ASK demodulator for biomedical implantable application. 508-511 - Elie Bou Assi
Refractory epilepsy: Localization, detection, and prediction. 512-515 - Zhongxia Shang, Yang Zhao, Yong Lian
Low power FIR filter design for wearable devices using frequency response masking technique. 516-519 - Te-Kuang Chiang, Ying-Wen Ko, Hong-Wun Gao, Yeong-Her Wang:
A new short-channel-effect-degraded subthreshold behavior model for elliptical gate-all-around MOSFET. 520-524 - Qianneng Zhou, Feihong Cheng, Hongjuan Li, Kai Yan, Wei Luo:
High-order curvature-compensated CMOS bandgap voltage reference. 525-528 - Quanwang Liu, Bo Zhang
A 3.7ppm/°C piece-wise compensated bandgap reference. 529-532 - Chi-Hsien Yen, Mehdi Nasrollahpour, Sotoudeh Hamedi-Hagh:
Low-power and high-frequency ring oscillator design in 65nm CMOS technology. 533-536 - Fangxu Lv, Jianye Wang, Dengjie Wang, Yongcong Liu, Ziqiang Wang:
Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology. 537-540 - Yan Chen, Xiaoling Tan, Boling Yu, Chunxia Li, Yan Guo:
A new all-in-one bandgap reference and robust zero temperature coefficient (TC) point current reference circuit. 541-544 - Jijian Shi, Tingting Mo:
A 2.4GHz T/R switch with ESD protection for WLAN 802.11 b/g/n applications. 545-548 - Haruo Kobayashi, Isao Shimizu, Nobukazu Tsukiji, Miho Arai, Kazuyoshi Kubo, Hitoshi Aoki:
Fundamental design tradeoff and performance limitation of electronic circuits based on uncertainty relationships. 549-552 - Lian Huai, Peng Li, Gerald E. Sobelman, David J. Lilja:
Stochastic computing implementation of trigonometric and hyperbolic functions. 553-556 - Yujie Chen, Ning Mei Yu, He Jiu Zhang, Keren Li, Nan Lyu:
A novel adaptive general current drive circuit. 557-560 - Yalong Pang, Ying Zhang, Jun Han, Xiaoyang Zeng:
Fp2 arithmetic acceleration based on modified Barrett modular multiplication algorithm. 561-564 - Yi Luo, Adrian Evans, Shi-Jie Wen, Rick Wong, GengSheng Chen:
IZIP: In-place zero overhead interconnect protection via PIP redundancy. 565-568 - Xianjie Long, Qin Wang, Jianfei Jiang, Nin Guan:
An on-chip circuit for timing measurement of SRAM IP. 569-572 - ChoongHyun Lee, Richard G. Southwick, Shogo Mochizuki, Paul Jamison, Ruqiang Bao, Rajan Pandey
Interface engineering of Si1-xGex gate stacks for high performance dual channel CMOS. 573-576 - Edward Yi Chang, Quang-Ho Luc, Huy-Binh Do
Performance improvement of InGaAs FinFET using NH3 treatment. 577-579 - Qiyuan Wang, Youwei Zhang
Layer thinning of MoS2 flakes by thermal annealing in air. 580-583 - Xingye Zhou, Xin Tan, Yuanjie Lv, Yuangang Wang, Xubo Song, Guodong Gu, Peng Xu, Hongyu Guo, Zhihong Feng, Shujun Cai:
Dynamic characteristics and related trapping effects of GaN-based Fin-MISHEMTs. 584-587 - Jingyu Liu, Yongyong Wang, Xunyong Yang, Fashun Yang, Kui Ma:
Analytical model of internal heat transfer of a power chip with through silicon via. 588-591 - Mingyue He, Sitong Bu, Daming Huang:
Surface effect on the current-voltage characteristics of back-gated MoS2 channel MOSFET. 592-595 - Xin Lou, Wenbin Ye:
Low complexity and low power multiplierless FIR filter implementation. 596-599 - Fei Gao, Xiaohua Feng, Ruochong Zhang
Dual-pulse nonlinear photoacoustic imaging: Physics, sensing and imaging system design. 600-603 - Wei Xu, Tianyuan Cheng, Chundong Wu, Nanshu Lu, Zeyu Yang, Yong Lian
Ultrathin flexible coils for wireless power and data link in biomedical sensors. 604-607 - Zhongxia Shang, Yang Zhao, Yong Lian
An APWM controlled LLC resonant converter for a wide input range and different load conditions. 608-611 - Xizhu Peng, Zuowei Mao, Ang Gao, Laishen Che, He Tang:
A low-power on-chip calibration technique for pipelined ADCs. 612-615 - Long Zhao, Bao Li, Yuhua Cheng:
A 6-bit 700-MS/s single-channel SAR ADC with low kickback noise comparator in 40-nm CMOS. 616-619 - Xinpeng Xing, Peng Zhu, Hui Liu, Wei Wang, Georges G. E. Gielen:
A power-efficient reconfigurable two-step VCO-based ADC for software-defined radio. 620-623 - Yongsheng Wang, Qiao Ye, Han Zhao, Xiaowei Liu:
A high-resolution pipeline time-to-digital converter in 0.18μm CMOS technology. 624-627 - Honghao Chu, Fule Li:
A 14bit 320MS/s pipelined-SAR ADC based on multiplexing of dynamic amplifier. 628-631 - Sujuan Liu, Ze Li, Zhenzhen Zhao, Yihui Fan:
All-digital background calibration technique of the channel-time-mismatch in a two-channel TIADC. 632-635 - Ruwu Xiao, Qiying Lei, Xuan Guo, Yuping Zhao:
A reference signal phase independent high precision timing skew mismatch estimation scheme for time interleaved ADC. 636-642 - Hsun-Wei Chan, Chang-Ting Wu, Chih-Wei Jen, Chun-Yi Liu, Wei-Che Lee, Shyh-Jye Jou:
A pseudo MMSE linear equalizer for 60GHz single carrier baseband receiver. 643-646 - Kazutoshi Kobayashi:
Highly-reliable integrated circuits for Gro. 647-650 - Fengwei An
Object-recognition VLSI for pedestrian detection in automotive applications. 651-653 - Peng Gao
A novel low-cost FPGA-based real-time object tracking system. 654-657 - Jifa Hao:
Hot carrier reliability in LDMOS devices. 658-661 - Hui Wang, Lingli Jiang, Ning Wang
The enhancement mode AlGaN/GaN high electron mobility transistor based on charge storage. 662-665 - Miaomiao Wang, Xin Miao, James H. Stathis, Richard G. Southwick:
Hot carrier reliability in ultra-scaled sige channel p-FinFETs. 666-669 - Jianfu Zhang, Meng Duan, Zhigang Ji, Weidong Zhang
Hot carrier aging of nano-scale devices: Characterization method, statistical variation, and their impact on use voltage. 670-673 - Zhongxun Guo, Wu Zan, Peng Zhou, Wenzhong Bao
A new device architecture based on two dimensional van der Waals heterostructures. 674-677 - Tongyang Ye, Ligang Hou, Shier Zhang, Jinhui Wang, Xiaohong Peng:
TSV modelling in 3D IC thermoelectric simulation. 678-681 - Kaijian Yuan, Xingming Zhang:
Low power mapping optimization of loops for dual-Vdd CGRAs. 682-685 - Hang Hu, Manxin Li, Zhiyuan Dai, Fan Ye
A 15MHz BW continuous-time ΔΣ modulator with high speed digital ELD compensation. 686-689 - Benqing Guo, Jun Chen, Hongpeng Chen, Xuebing Wang, Chang Liu:
An inductorless noise-cancelling CMOS LNA using wideband linearization technique. 690-693 - Xubo Song, Cui Yu, Zezhao He, Qingbin Liu, Tingting Han, Shaobo Dun, Yuanjie Lv, Shujun Cai, Zhihong Feng:
Design and realization of a X-band graphene amplifier MMIC. 694-697 - Hongwei Zhu, Qiuliang Li, Hao Sun, Zhipeng Wang, Ran Liu, Yi Liu:
Ultra low loss and high linearity RF switch using 130nm SOI CMOS process. 698-701 - Jin Yan, Dongsheng Liu, Xuecheng Zou, Bangdi Xu:
A novel positive-feedback read scheme with tail current source of STT-MRAM. 702-705 - Chen Jiao, Zunchao Li, Chuang Wang
A single-inductor MIMO buck-boost converter with inductor-peak-current PFM control for multiple energy harvesting. 706-709 - Tongzhou Qu, Zibin Dai, Longmei Nan, Wei Li, Anqi Yin:
An area-efficient interconnection network for coarse-grain reconfigurable cryptographic array. 710-713 - Sotoudeh Hamedi-Hagh:
Extraction of circuit transfer functions with SuTra analyses. 714-717 - Linquan Lyu, Takeshi Yoshimura:
A force directed partitioning algorithm for 3D floorplanning. 718-721 - Yifan Gao, Weigang Xu, Chenyang Kong, Zhangwen Tang:
A broadband power detector with temperature and process compensation. 722-725 - Pei-Yu Chen, Lan-Da Van, Hari C. Reddy, I-Hung Khoo:
Type-3 2-D multimode IIR filter architecture and the corresponding symmetry filter's error analysis. 726-729 - Binbin Lyu, Wengao Lu, Sijia Yang, Zhongjian Chen, Yacong Zhang:
A self-adaptive digital calibration technique for multi-channel high resolution capacitive SAR ADCs. 730-733 - Ze He, Xiaowen Chen:
Design and implementation of high-speed configurable ECC co-processor. 734-737 - Chaoyang Li, Qin Wang, Jianfei Jiang, Nin Guan:
A metastability-based true random number generator on FPGA. 738-741 - Liwen Zhu, Xiaole Cui, Xiang Li, Xiaoxin Cui:
A signal noise separation method for the instant mixing linear and nonlinear circuits with MISEP algorithm. 742-745 - Kuimin Zhang, Xiaole Cui, Xiaoxin Cui:
A design of high performance full adder with memristors. 746-479 - Fubiao Cao, Yongzhen Chen, Zhiyuan Dai, Fan Ye, Junyan Ren:
An input buffer for 12bit 2GS/s ADC. 750-753 - Fubiao Cao, Yongzhen Chen, Yuefeng Cao
A proved dither-injection method for memory effect in double sampling pipelined ADC. 754-757 - Shuang Cui, Tianzhao Liu, Haoran Gong, Bingyan Hu, Yuchun Chang:
A high performance switched-capacitor programmable gain amplifier design in 0.18μm CMOS technology. 758-761 - Liang Zhang, Xu Cheng, Tong Xiaodong, Xianjin Deng:
High voltage charge pump circuit using vertical parallel plate capacitors. 762-764 - Shu Yang, Minghang Liu, Yusong Mu, Yuchun Chang:
A 14-bit 5 MS/s split non-binary SAR ADC. 765-768 - Shijia Zhu, Yu Wang, Fan Ye, Jun Xu:
A clock interpolation structure using DLL for clock distribution in ADC. 769-772 - Xiao Zhou, Ping Luo, Linyan He, Tiancheng Xiao:
A radiation-hard waffle layout for BCD power MOSFET. 773-775 - Weigang Xu, Yifan Gao, Xiaodong Liu, Zhangwen Tang:
A 18 mW 12 bit 50 MS/s SHA-less pipelined ADC. 776-779 - Sijia Yang, Lingzi Luo, Wengao Lu, Guangyi Shi, Binbin Lyu, Yuze Niu, Yacong Zhang, Zhongjian Chen:
A 16-bit two-step pixel-level ADC for 384∗288 infrared focal plane array. 780-783 - Yixia Liu, Xiaoxin Cui, Jian Cao, Xing Zhang:
A hybrid fault model for differential fault attack on AES. 784-787 - Xiaolei Wang, Dongming Qu, Yu-Kun Song, Duoli Zhang:
Design and implementation of homogeneous multi-core system. 788-791 - Can Wei, Yu-Kun Song, Duoli Zhang:
A chain-multiplier for large scale matrix multiplication. 792-795 - Xiangyun Deng, Jin Sha, Xiaotian Zhou, Xiaohu You, Chuan Zhang:
Joint detection and decoding for polar-coded OFDM-IDMA systems. 796-799 - Licheng Xu, Xinchi Gao, Jing Jin:
A high-speed low-power charge pump with dynamic current matching. 800-803 - Shaoqin Yao, Litong Liu, Jing Jin:
A passive mixer-first receiver with negative feedback for impedance matching. 804-806 - Yukuai Chen, Jian Cao, Zhang Qihui, Yuan Wang
A novel equivalent circuit model of the surge wave generator. 807-810 - Tomotaka Inoue, Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
Designing hardware trojans and their detection based on a SVM-based approach. 811-814 - Xiaopei Chen, Sheng Wang, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
A light-weight energy-efficient resilient circuit for variation tolerance. 815-818 - Qiulong Hong, Xiubo Liu, Shaodong Wang:
Design of Ka band bandpass filter using silicon micromachined technology. 819-821 - Hao Zhang, Ahmed Raslan, Slim Boumaiza, Lan Wei:
Physics based compact model of GaN HEMT with an efficient parameter extraction flow. 822-825 - Xiaojiao Ren, Ming Zhang, Nicolas Llaser:
CMOS 0.35μm implementation of time-domain measurement of resonator's quality factor. 826-829 - Xiaofei Hu, Xiao Ge, Ting Yi, Danzhu Lu, Zhiliang Hong:
A 1.2V output RF energy harvester with a harvesting-efficiency tracking circuit. 830-834 - Manxin Li, Hang Hu, Zhiyuan Dai, Fan Ye
A 12bit asynchronous SAR-incremental sub-range ADC. 835-838 - Zhaozhong Ying, Chong Luo, Xiaolei Zhu:
A scalable hardware architecture for multi-layer spiking neural networks. 839-842 - Dan Liu, Feng Gao, Liguang Hao, Jianxin Liao:
32-Channel ROIC for X-ray imaging system. 843-846 - Kaixuan Zhang, Li Ding, Yujie Cai, Wenbo Yin, Fan Yang, Jun Tao, Lingli Wang:
A high performance real-time edge detection system with NEON. 847-850 - Wenfeng Dong, Dong Liu, Shun Xu, Bing Chen, Yi Zhao:
Demonstrate high Roff/Ron ratio and forming-free RRAM for rFPGA application based on switching layer engineering. 851-854 - Zhi-Wen Chen, Hui-Hong Zhang:
Power optimization on MUX mapped circuits. 855-858 - Xihan Gu, Yun Chen, Xiaofeng Wu:
Active ego-noise control based on metamaterial in small-size robot. 859-862 - Xiaojing Zha, Yinshui Xia:
Genetic algorithm based on divide-and-conquer strategy for defect-tolerant CMOL mapping. 863-866 - (Withdrawn) Application of LDPC codes on PUF error correction based on code-offset construction. 867-870
- Mehdi Nasrollahpour, Sotoudeh Hamedi-Hagh:
High speed, low offset, low power differential comparator with constant common mode voltage. 871-874 - Yuanyuan Xu, Wei Li, Dan Wu, Ning Li:
A programmable divider with extended division range for 24GHz FMCW frequency synthesizer. 875-878 - Weiye Cai, Hongge Li:
Large-array high-density active microelectrodes array for neural signal recording. 879-882 - Yunhao Xu, Yingjie Lao, Weiqiang Liu, Xiaohu You, Chuan Zhang:
DC MUX PUF: A highly reliable feed-back MUX PUF based on measuring duty cycle. 883-886 - Yutong Wang, Hongjiang Wu, Jing Li, Xingchang Fu:
The D-band MMIC LNA circuit using 70nm InP HEMT technology. 887-890 - Yuchen Yao, Zhiqian Zhang, Zhen Yang, Jian Wang, Jinmei Lai:
FPGA-based convolution neural network for traffic sign recognition. 891-894 - Zengxin Liu, Shaowei Zhen, Shuiqing Xi, Xinjiang Gao, Lei Yang, Jiongwei Zheng, He Tang, Yajuan He, Ping Luo, Bo Zhang
A digital-assistant time-to-amplitude converter with dynamic range improvement. 895-899 - Chenyang Wang, Yilei Shen, Pan Xue, Zhiliang Hong:
The implement of digital front end in all-digital quadrature RF transmitter. 900-903 - Weihong Xu, Zhongfeng Wang, Xiaohu You, Chuan Zhang:
Efficient fast convolution architectures for convolutional neural network. 904-907 - Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors. 908-911 - Wenfeng Zhao, Ang Li, Yi Wang
Analysis and design of energy-efficient data-dependent SRAM. 912-915 - Ling Chen, Yanan Sun, Weifeng He:
Low-power single-phase clocked redundant-transition-free flip-flop design with conditional charging scheme. 916-919 - Jun Zhou, Tony Tae-Hyoung Kim, Yong Lian
Near-threshold processor design techniques for power-constrained computing devices. 920-923 - Gong Xiaowu:
Optimization compensation for primary-side-regulated flyback converters in continuous-conduction-mode and discontinuous conduction mode. 924-927 - Nobuyuki Otsuka, Yasufumi Kawai, Shuichi Nagai:
Recent progress in GaN devices for power and integrated circuit. 928-931 - Zekun Zhou, Jianwen Cao, Yue Shi, Bo Zhang
A high-precision voltage regulator with dynamic load technique and overcurrent protection. 932-935 - Yang Liu
Backscattering in multicycle Q-modulation for bio-implants wireless power transfer. 936-939 - Xiao Ge, Xiaofei Hu, Yajie Qin, Zhiliang Hong:
A single inductor tri-input dual-output buck-boost DC-DC converter with MPPT for multi-source energy harvesting. 940-943 - Xin Li, Yujie Cai, Jun Han, Xiaoyang Zeng:
A high utilization FPGA-based accelerator for variable-scale convolutional neural network. 944-947 - Lintao Liu, Yuhan Gao, Haoming Du:
A novel mixed reconfigurable system on chip based on field programmable analog array. 948-952 - Jianwei Yang, Weizhen Wang, Zhicheng Xie, Jun Han, Zhiyi Yu, Xiaoyang Zeng:
Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design. 953-956 - Yongxin Cong, Ming Xu, Dan Zhao, Dongping Wu:
A 3600 × 3600 large-scale ISFET sensor array for high-throughput pH sensing. 957-960 - Shusen Jing, Anlan Yu, Xiao Liang, Xiaohu You, Chuan Zhang:
Uniform belief propagation processor for massive MIMO detection and GF(2n) LDPC decoding. 961-964 - Yewen Ni, Xiaoxin Cui, Yuanning Fan, Qiankun Han, Kefei Liu, Xiaole Cui:
Design of router for spiking neural networks. 965-968 - Qinmiao Kang, Zhifeng Xie, Yongquan Liu, Ming Zhou:
A fuel injection control SoC for Diesel Engine Management System. 969-972 - Wenjian Yu, Taotao Lu:
Efficient algorithms for resistance and capacitance calculation problems in the design of flat panel display: [Invited paper]. 973-976 - Qi Chen, Cheng Li, Fei Lu, Chenkun Wang, Feilong Zhang, Tianru Wu, Xiaoming Xie, Kun Zhang, Xinxin Li, Jimmy Ng, Ya-Hong Xie, Yuhua Cheng, Albert Z. Wang:
Characterization of single-crystalline graphene ESD interconnects. 977-980 - Tapas K. Maiti
Compact modeling approach for electro-mechanical system simulation. 981-984 - Yongming Ding, Wei Jin, Guanghui He, Weifeng He:
Short path padding with multiple-Vt cells for wide-pulsed-latch based circuits at ultra-low voltage. 985-988 - Kaixuan Zhang, Zhihua Feng, Hao Zhou:
A fast HDL model for full-custom FPGA verification. 989-992 - Kiat Seng Yeo
Micro-LED arrays for display and communication: Device structure and driver architecture. 993-996 - Jun Chen, Qian Hou, Zhanjiang Guo, Yuheng Nie, Zeng Peng, Robert K. F. Teng:
A biomedical microfluidic mixer in MEMS application using inkjet. 997-1000 - Huiyuan Lu, Hongge Li:
A bulk-driven pixel circuit with wide data voltage range for OLEDoS microdisplays. 1001-1004 - Yuze Niu, Wengao Lu, Yacong Zhang, Shanzhe Yu, Zhongjian Chen:
A low-power self-calibration digital-output CMOS temperature sensor with ±0.1°C inaccuracy from -40°C to 85°C. 1005-1008 - Chengying Chen, Liming Chen, Zhenli Lai:
A 58-dB SNDR 1.32-mW chopper-stabilized analog front-end for graphene hall element detecting application. 1009-1012 - Jinna Yan, Bharatha Kumar Thangarasu, Kiat Seng Yeo
RF mixer design techniques using GaAs process. 1013-1016 - Chaojiang Li, Min Wang, Taiyun Chi, Arvind Kumar, Myra Boenke, Dawn Wang, Ned Cahoon, Anirban Bandyopadhyay, Alvin J. Joseph, Hua Wang
5G mm-Wave front-end-module design with advanced SOI process. 1017-1020 - Jiaqi Wei, Liang Chang
Ultrafast spintronic integrated circuits. 1021-1024 - Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz
Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network. 1025-1028 - Chuan Zhang, Weihong Xu:
Neural networks: Efficient implementations and applications. 1029-1032 - Weihong Xu, Xiaohu You, Chuan Zhang:
Using Fermat number transform to accelerate convolutional neural network. 1033-1036 - Chao Huang, Siyu Ni, Gengsheng Chen:
A layer-based structured design of CNN on FPGA. 1037-1040 - Wei Yu, Jing Chang, Cheng Yang, Limin Zhang, Han Shen, Yongquan Xia, Jin Sha:
Automatic classification of leukocytes using deep neural network. 1041-1044 - Yangcan Zhou, Jun Lin, Zhongfeng Wang:
Energy efficient SVM classifier using approximate computing. 1045-1048 - Francis Balestra:
Ultra low power and high performance nanoelectronic devices. 1049-1052 - Mingqiang Huang, Xiong Xiong, Tiaoyang Li, Yanqing Wu:
High performance transistors based on two dimensional materials. 1053-1056 - Rui Zhang, Jinghui Han, Junkang Li, Xiaoyu Tang, Yi Zhao:
NiGe metal source/drain Ge pMOSFETs for future high performance VLSI circuits applications. 1057-1060 - Peng Lu, Po-Yen Chien, Xicheng Duan, Jason C. S. Woo:
Deeply scaled VLSI analog transistor design and optimization. 1061-1064 - Masanori Hashimoto
Toward real-time 3D modeling system with cubic-millimeters wireless sensor nodes. 1065-1068 - Yiqian Cai, Jin Sha, Shusen Jing, Xiaohu You, Chuan Zhang:
Joint detection and decoding for non-binary LDPC coded MIMO systems. 1069-1072 - Xiaozhen Liu, Hongxiang Xie, Jin Sha, Feifei Gao, Shi Jin, Xiaohu You, Chuan Zhang:
The VLSI architecture for channel estimation based on ADMA. 1073-1076 - Xiao Liang, Yechao She, Harish Vangala, Xiaohu You, Chuan Zhang, Emanuele Viterbo
An efficient successive cancellation polar decoder based on new folding approaches. 1077-1080 - Anqi Yin, Zibin Dai, Longmei Nan, Wei Li:
RC6 architecture-adaptive implementation for coarse-grained reconfiguration array. 1081-1085 - Hengliang Xiang, Liang Chen, Wei Xu:
DRFNet: A lightweight and high accuracy network for resource-limited implementation. 1086-1089 - Guoqing Sun, Xiaohong Peng, Jun Zhao, Rui Wang, Xiaodan Li:
Design of digital control unit for implantable stimulator chip. 1090-1093 - Andreas Kaiser
Digital RF transmitter architectures exploiting FIRDACs in various configurations. 1094-1097 - Minoru Fujishima
Terahertz CMOS transceiver for tera-bps wireless link. 1098-1100 - Qinmiao Kang, Zhifeng Xie, Yongquan Liu, Ming Zhou:
125KHz wake-up receiver and 433MHz data transmitter for battery-less TPMS. 1101-1104 - Hui Zhao, Cuncai Zhang, Jie Liang, Jun Zeng, Yun Deng, Dingyang Chen, Guojun He, Qingfeng Luo:
A low power high integrated BLE transceiver. 1105-1108 - Yu Li, Ziqian Wang, Song Chen, Fujiang Lin:
A low-power digital GFSK receiver with mid-value filtering frequency offset estimator and soft anti-overlap slicer. 1109-1112 - Yun Yin, Tong Li, Xiaoyong Xue:
A 1.0-3.0GHz LTE transmitter with CIM enhancement. 1113-1116 - Cong Chen, Kim Batselier
Tensor-network-based predistorter design for multiple-input multiple-output nonlinear systems. 1117-1120 - Qing-An Huang
Towards an LC passive wireless sensor platform. 1121-1024 - Sid Zarabi, Egon Fernandes, Isabel Rua, Armaghan Salehian, Hélène Debéda, David Nairn, Lan Wei:
Design and development of a self-contained and non-invasive integrated system for electricity monitoring applications. 1125-1128 - Nan Wang, Hengxiao Wang, Yue Jin, Jiongyao Ye:
Integrating operation scheduling and binding for functional unit power-gating in high-level synthesis. 1129-1132 - Pei-Yu Chen, Lan-Da Van, I-Hung Khoo, Hari C. Reddy:
New 2-D quadrantal- and diagonal-symmetry filter architectures using delta operator. 1133-1136 - Kazuo Tsutsui, Kuniyuki Kakushima, Takuya Hoshii
3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat). 1137-1140 - Kazuhiko Endo
Advanced FinFET technologies for boosting SRAM performance. 1141-1144 - Zong-You Hou, Hsiu-Chun Tsai, Chua-Chin Wang:
High-voltage bidirectional current sensor. 1145-1146
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