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CICC 2024: Denver, CO, USA
- IEEE Custom Integrated Circuits Conference, CICC 2024, Denver, CO, USA, April 21-24, 2024. IEEE 2024, ISBN 979-8-3503-9406-1
- Yakun Sophia Shao:
Next-Generation Domain-Specific Accelerators: From Hardware to System. 1-5 - J. Liu, Z. Xie, X. Wang, X. Liu, X. Qiao, J. Fan, H. Qin, C. Guo, J. Xiao, S. Lin, J. Zhou:
BioWAP: A Reconfigurable Biomedical AI Processor with Adaptive Processing for Co-Optimized Accuracy and Energy Efficiency. 1-8 - Heyu Ren, Liangjian Lyu, Binbin Chen, Chuanjin Richard Shi:
A -104dBm-Sensitivity Receiver with Shared Wireless LO and Envelope-Tracking Mixer Achieving -46dB SIR. 1-2 - Yingping Chen, Kaiwen Shen, Qing Yuan, Ming Liu:
A Closed-Loop EMI Regulated GaN Power Converter with 500MHz-Sampling-Bandwidth In-Situ EMI Sensing and 9kHz-Resolution Global Excess-Spectrum Modulation. 1-2 - Danilo Manstretta:
Interferer-Tolerant RX Front-End Architectures. 1-8 - Wei Zhang
, Minglei Zhang, Yan Zhu, R. P. Martins, Chi-Hang Chan:
A PVT-Robust 8b 20GS/s Time-Interleaved SAR ADC with Quantization-Embedded Current-Mode Buffer and Differ-Based Dither Timing Skew Calibration. 1-2 - Martin Lefebvre
A Mixed-Signal Near-Sensor Convolutional Imager SoC with Charge-Based 4b-Weighted 5-to-84-TOPS/W MAC Operations for Feature Extraction and Region-of-Interest Detection. 1-2 - Yarallah Koolivand, Alireza Mosalmani, Yasser Rezaeiyan
A 65nm 3mA 0.14-m-Accuracy TDR Based Leak Detection SoC for District Heating Networks with I/C Calibration Technique. 1-2 - Tian Xie, Ken Li, Tzu-Han Wang, Wei-En Lee, Engin Esen, Dong Suk Kang, Shaolan Li:
An 82dB-SNDR Input-Driving-Relaxed Noise-Shaping SAR with Amplifier-Reused In-Loop Buffering and NTF Leakage Reshaping. 1-2 - Sun-Yang Tay, Victor Adrian, Rouli Fang, Yanshan Xie, Joseph S. Chang:
A 134-μW 50-MHz Quasi-Dynamic Comparator with A Novel Clock-Free Regenerative Latch. 1-2 - Yifei Xia
An Integrated Burst-Mode 2R Receiver Employing Fast Residual Offset Canceller for XGS-PON in 40-nm CMOS. 1-2 - Guodong Yin, Yiming Chen, Mingyen Lee, Xirui Du, Yue Ke, Wenjun Tang, Zhonghao Chen, Mufeng Zhou, Jinshan Yue, Huazhong Yang, Hongyang Jia, Yongpan Liu, Xueqing Li:
A 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM. 1-2 - Yatao Peng, Jad Benserhir, Yating Zou, Edoardo Charbon:
A Cryogenic Double-IF SSB Controller with Image Suppression and On-Chip Filtering implemented in 130nm SiGe BiCMOS Technology for Superconducting Qubit Control. 1-2 - Zhaonan Lu
A 188.6-μW Continuous-time Incremental Delta-Sigma ADC with Extended Counting achieving 95.2-dB SNDR and 175.4-dB FoMSNDR. 1-2 - Longjie Zhong, Pengpeng Shang, Shubin Liu, Wenfei Cao, Lichen Feng, Yuhua Liang, Zhangming Zhu:
A 0.64mm2Sensor Size, 32.5μg/√Hz Noise Floor, High Efficiency MEMS Capacitive Accelerometer Using High-Voltage Pulse Excitation Technique. 1-2 - Jihwan Kim, Ariel Cohen, Mike Peng Li, Ajay Balankutty, Sandipan Kundu, Ahmad Khairi, Yoel Krupnik, Yoav Segal, Marco Cusmai, Dror Lazar, Ari Gordon, Noam Familia, Kai Yu, Yutao Liu, Matthew Beach, Priya Wali, Hsinho Wu, Masashi Shimanouchi, Jenny Xiaohong Jiang, Zhiguo Qian, Kemal Aygun, Itamar Levin, Frank O'Mahony:
Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging. 1-8 - Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, John F. Bulzacchelli, Marcel A. Kossel, Pier Andrea Francese, Thomas Morf, Jonathan E. Proesel, Herschel A. Ainspan, Matthias Brändli, Mounir Meghelli:
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration. 1-8 - Mohamed Eleraky, Jeongsoo Park, Basem Abdelaziz Abdelmagid, Naga Sasikanth Mannem, Hua Wang:
A Mm-Wave Phase-Time Co-Apertured Transceiver Array with Beam Squinting Mitigation for Wideband Beamforming/Spatial-Nulling. 1-2 - Minyoung Kang, Sunghoon Kim, Youngmin Park, Sangsu Jeong, Dongsuk Jeon:
A 28nm All-Digital Droop Detection and Mitigation Circuit Using a Shared Dual-Mode Delay Line with 14.8% VminReduction and 42.9% Throughput Gain. 1-2 - Nan Sun:
Welcome from the CICC Committee! 1 - Minil Kang, Minseong Um, Jongun Won, Jaehyeon Kang, Sangjun Hong, Narae Han, Sangwook Kim, Sangbum Kim, Hyung-Min Lee:
An Analog Neuromorphic On-Chip Training System with IGZO TFT-Based 6T1C 367-State Synaptic Memory Achieving 0.99-R2 Linearity and 104-Times Enhanced Retention Time. 1-2 - Wenning Jiang, Yunbin Luo, Peizhe Li, Ji Guo, Chixiao Chen, Qi Liu:
A 13b 500MS/s Dual-Residue Pipelined-SAR ADC with One-Way Switching Capacitive Interpolation and Background Offset Calibration. 1-2 - Seungjun Song, Dongsik Lee, Hyungil Chae:
A 50MHz-BW 168.8dB-FoM 2x Time-Interleaved Bandpass Noise Shaping SAR ADC Using Passive Filter. 1-2 - Qingzhe Zhang, Yi Lai, Keping Wang:
A 32-to-38GHz Variable-Gain Phase Shifter with Impedance-Invariant Vector Modulation Achieving RMS Phase/Amplitude Errors of 0.33○/0.10dB in PS mode and 0.23○/0.08dB in VGA mode. 1-2 - Jiacheng Hao, Qingsen Zhuang, Junhang Zhang, Xiaojin Zhao:
A 98fJ/Bit Current-Starved-Ring-Oscillator-Based TRNG with High PVT Tolerance and Resilience to Frequency Injection Attack Up to 1V. 1-2 - Zehao Li, Yuncheng Lu, Anh Tuan Do, Tony Tae-Hyoung Kim:
A 4.2pJ/Pixel 480 fps Stereo Vision Processor with Pixel Level Pipelined Architecture and Two-Path Aggregation Semi-Global Matching. 1-2 - Chi-Hang Chan, Minglei Zhang, Yuefeng Cao
The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs. 1-8 - Ahmed G. Gadelkarim, Patrick P. Mercier:
A 18.2mW Subsampling mm-Wave Receiver Employing a Subtractive Anti-Aliasing Active Bandstop Filter at 23GHz. 1-2 - Gourab Barik, Baibhab Chatterjee, K. Gaurav Kumar, Shreyas Sen:
A 65nm 21.9pJ/Sa Pixel to PWM Conversion SoC with Time-domain Body Communication for ULP Body-Worn Video Sensor Nodes with Distributed Real-Time Inference. 1-2 - Haikang Diao, Haoyang Luo, Jiahao Song, Bocheng Xu, Runsheng Wang, Yuan Wang, Xiyuan Tang:
A 28nm 128TFLOPS/W Computing-In-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI. 1-2 - Haoming Xin, Meiyi Zhou
A 10V Compliant 16-Channel Stimulator ASIC with sub-10nA Mismatch and Simultaneous ETI Sensing for Selective Vagus Nerve Stimulation. 1-2 - Cong Ding, Mingxiang Gao, Anja K. Skrivervik
A 49.8mm2 Fully Integrated, 1.5m Transmission-Range, High-Data-Rate IR-UWB Transmitter for Brain Implants. 1-2 - Ke Li, Xianyu Congzhou, Liang Qi, Mingqiang Guo, Rui Paulo Martins, Sai-Weng Sin:
A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering. 1-2 - Xinling Yue, Yiwei Zou, Sijun Du:
A Resonant Synchronized Switch Harvesting Rectifier with Bias-Flip Charge Recycling for Piezoelectric Energy Harvesting Achieving 13.9x Power Enhancement. 1-2 - Ryan Burns, Austin Wiechmann, Pardis Sadeghi, Nader Lobandi, Nader Fathy, Rui Huang, Nian Sun, Patrick P. Mercier:
A 24.4μW Room Temperature Gas Sensor Based on Molecularly Imprinted Polymers Demonstrating SARS-Cov-2 and D-Glucose Aerosol Sensing. 1-2 - Qiaobo Ma, Huihua Li
A Multi-Phase Multi-Path Hybrid Buck Converter for 9-48V to 0.8-1.2V Conversion with Improved DCR-Loss Reduction and Alleviated CFLY Current Gathering Achieving 88.3% Peak Efficiency and 176A/cm3Density. 1-2 - Yanqiao Li, Ziyu Xia, Jason T. Stauth
A Pseudo-Adiabatic Switched-Capacitor Gate Driver for Si and GaN FETs Achieving >5x Power Reduction. 1-2 - Lingxin Meng, Menglian Zhao, Zhichao Tan:
A 93.6dB-SNDR 5kHz-BW Fully Dynamic Hybrid CT-DT Noise Shaping SAR ADC. 1-2 - Qiujin Chen
A 1.58-nA CEPE-Based Hill-Climbing MPPT Technique with Compensated Ton Achieving 67.3% Efficiency at 10-nA Lload and > 97% MPPT Efficiency at VCR from 2 to 6. 1-2 - Xinling Yue, Sijun Du:
A Single-Stage Bias-Flip Regulating Rectifier with Fully-Digital Fast-MPPT for Piezoelectric Energy Harvesting Achieving 9.3X Power Enhancement and 92.5% End-to-End Efficiency. 1-2 - Eunhwan Kim
A 10T2C Capacitive SRAM-based Computing-In-Memory Macro with Array-Embedded DAC and Shift-and-Add Functions. 1-2 - Aobo Li
A 40nm 1.26µ/Op Energy-Efficient CRYSTALS-KYBER Post-Quantum Crypto-Processor with Comprehensive Side Channel Security Analysis and Countermeasures. 1-2 - Wei He, Puvi Bai, Hongyang Luo, Zhenghao Jin, Han Wu, Junyi Zhang, Xingchen Chao, Haiqi Liu, Yajuan He, Qiang Li:
131TOPS/W 8b ACIM Exploiting Weight-Embedded Auto-Accumulation and Supporting Symmetric Quantization Networks. 1-2 - Runtao Huo, Dingguo Zhang, Jing Jin, Jianjun Zhou, Hui Wang:
A 16MHz CMOS RC Frequency Reference with ±125ppm Inaccuracy from -40°C to 85°C Enabled by a Capacitively Modulated RC Time Constant (CMT) Generation and a Die-to-Die Error Removal (DDER) Technique. 1-2 - Simone Mattia Dartizio, Michele Rossoni
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector. 1-2 - Pietro Salvi, Simone Mattia Dartizio, Michele Rossoni
A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC. 1-2 - Hanyu Shi, Mingchao Liang, Jie Zhu, Zhuang Zhang, Peng Cao, Jiawei Xu, Zhiliang Hong:
A 2.4-to-240W, 95.04% Peak Efficiency LLC Isolate Converter Controller with Symmetric Pulse-Width Balancing and Fixed-Period Hysteresis Burst Control. 1-2 - Qifeng Huang, Siji Huang, Yanhang Chen, Yifei Fan
A 16b 5MS/s 93.7dB-SNDR SAR ADC with a Split Sampling Technique and SRM-Assisted Self-Calibration. 1-2 - Yizhuo Wang, Hao Xu, Guoyu Li, Shuai Liu, Yan Liu, Rui Yin, Hui Pan, Na Yan:
An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS. 1-2 - Junwei Huang, Zhiguo Tong
A Fast-Slow Two-Module DC-DC Solution with Transient and Efficiency Improvements for 2.5D/3D Integration. 1-2 - Sikai Chen, Jintao Xue, Yihan Chen, Yuean Gu, Haoran Yin, Shenlei Bao, Guike Li, Binhao Wang, Nan Qi:
A 2λ×100 Gb/s Optical Receiver with Si-Photonic Micro-Ring Resonator and Photo-Detector for DWDM Optical-IO. 1-2 - Amitesh Sridharan, Fan Zhang
SP-IMC: A Sparsity Aware In-Memory-Computing Macro in 28nm CMOS with Configurable Sparse Representation for Highly Sparse DNN Workloads. 1-2 - Walker J. Turner, John W. Poulton, Yoshinori Nishi, Xi Chen, Brian Zimmer, Sanquan Song, John M. Wilson, William J. Dally, C. Thomas Gray:
Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications. 1-7 - Siddharth Saxena, Sudhir S. Kudva, Vijay Srinivasan, Miguel Rodriguez, Walter Li, Shalimar Rasheed, Gaurav Ajwani, Tezaswi Raja, Santosh A, C. Thomas Gray:
A Distributed Power Supply Scheme with Dropout Voltage in Range 6mv-500mv and a Low Overhead Retention Mode. 1-2 - Alireza Dabbaghian, Hossein Kassiri:
Modular Flexible 80-dB-DR Artifact-Resilient EEG Headset with Distributed Pulse-Based Feature Extraction and Multiplier-Less Neuromorphic Boosted Seizure Classifier. 1-2 - Dongfang Pan, Weiwei Xu, Xiangfeng Wu, Aoyang Li, Lin Cheng:
A 24V-to-20V 6W 73.2%-Peak-Efficiency Isolated DC-DC Converter Using a Transformer-Based Supply-Generating Technique. 1-2 - Gönenç Berkol, Matt Whitney:
Circuit Design Techniques for High-Voltage Comparators and Amplifiers. 1-8 - Suyang Song, Alessandro Novello, Taekwang Jang:
Challenges and Innovations in Fully Integrated DC-DC Converters for IoT and Modern Computing Platforms. 1-8 - Marco Fattori, Enrico Genco, Carmine Garripoli, Mohammad Zulqarnain, Kris Myny, Eugenio Cantatore:
Advanced Sensing Systems Exploiting the Integration of Flexible and Large-Area TFTs with Si-CMOS Technology. 1-8 - Chang Eun Song, Yidong Li, Amardeep Ramnani, Pulkit Agrawal, Purvi Agrawal, Sung-Joon Jang, Sang-Seol Lee, Tajana Rosing, Mingu Kang:
52.5 TOPS/W 1.7GHz Reconfigurable XGBoost Inference Accelerator Based on Modular-Unit-Tree with Dynamic Data and Compute Gating. 1-2 - Yuyang Wang, Songli Wang, Robert Parsons
Silicon Photonics Chip I/O for Ultra High-Bandwidth and Energy-Efficient Die-to-Die Connectivity. 1-8 - Chaoming Fang, Ziyang Shen, Shiqi Zhao, Chuanqing Wang, Fengshi Tian, Jie Yang, Mohamad Sawan:
A 0.078 pJ/SOP Unstructured Sparsity-Aware Spiking Attention/Convolution Processor with 3D Compute Array. 1-2 - Zonglin Ye, Xinlin Geng, Zhixiang Shi, Hongyang Zhang, Qian Xie, Zheng Wang:
A 6.8-to-14.4GHz Octave-Tuning Fractional-N Charge-Pump PLL with Slide-Dithering-Based Background DTC Nonlinearity Calibration for Near-Integer Fractional Spur Mitigation Achieving 78fs RMS Jitter and -258.6dB $\text{FoM}_{\mathrm{T}}$. 1-2 - Deniz Umut Yildirim, Jaeyoung Jung, Amr Elsakka, Giuseppe Moschetti, Miguel M. Lopez, Jonas Hansryd, Tomás Palacios, Anantha P. Chandrakasan:
A 0.7cm2 3.5GHz, -31 dBm Sensitivity Batteryless 5G Energy Harvester Backscattering Chip for Asset Identification in IoT-Enabled Warehouses. 1-2 - Chengyu Huang, Kezhuo Ma, Sihao Chen, Jiaxuan Fan, Nan Sun, Huazhong Yang, Xueqing Li:
A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS. 1-2 - Wenyu Peng, Xinling Yue, Willem D. van Driel, Guoqi Zhang, Sijun Du:
A 70-V Fully Integrated Dual-SSHC Rectifier for Triboelectric Energy Harvesting with Full-Digital Duty-Cycle-Based MPPT Achieving 598% Power Extraction Enhancement. 1-2 - Petar Barac, Matthew Bajor, Tanbir Haque, Peter R. Kinget:
A Beamforming Receiver Using a Time-Modulated LO-Path Vector Modulator Achieving Amplitude and Phase Control with 0.2 dB RMS Gain Error and 1.4 Degree RMS Phase Error. 1-2 - Jaehyun Lee, Dong-gu Choi, Minyoung Song
BEE-SLAM: A 65nm 17.96 TOPS/W 97.55%-Sparse-Activity Hybrid Mixed-Signal/Digital Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics. 1-2 - Chao Zhang, Yongxiang Guo, Dawid Sheng, Zhixiong Ma, Chao Sun, Yuwei Zhang, Wenxin Zhao, Fenyan Zhang, Tongfei Wang, Xing Sheng, Milin Zhang:
A Closed-Loop Brain-Machine Interface SoC Featuring a 0.2μJ/class Multiplexer Based Neural Network. 1-2 - Pranav O. Mathews
A 65nm and 130nm CMOS Programmable Analog Standard Cell Library for Scalable System Synthesis. 1-2 - Jose De Sales Filho, Hossein Kassiri, Xilin Liu, Roman Genov:
Artificially Intelligent Closed-Loop Neurostimulators: Trade-Offs between Local and Remote Computing. 1-7 - Jie Li, Linxiao Shen, Siyuan Ye, Jihang Gao, Jiajia Cui, Xinhang Xu, Zhuoyi Chen, Yaohui Luan, Yuanxin Bao, Ru Huang, Le Ye:
An 8b 1GS/s SAR ADC with Metastability-Based Resolution/Speed Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist Input. 1-2 - Youngin Kim, Laurenz Kulmer, Killian Keller, Jeongsoo Park, Basem Abdelaziz Abdelmagid, Kyung-Sik Choi, Dongwon Lee, Yuqi Liu, Juerg Leuthold, Hua Wang:
A Co-Integrated Optical Phased Array, Mach-Zehnder Modulator and Mm-Wave Driver for Free-Space Communication. 1-2 - Fuzhan Chen
A 56-Gbaud 7.3-Vppd Linear Modulator Transmitter with AMUX-Based Reconfigurable FFE and Dynamic Triple-Stacked Driver in 130-nm SiGe BiCMOS. 1-2 - Maitreyi Ashok, Saurav Maji, Xin Zhang, John Cohn, Anantha P. Chandrakasan:
A Secure Digital In-Memory Compute (IMC) Macro with Protections for Side-Channel and Bus Probing Attacks. 1-2 - Longjie Zhong, Chengyue Li, Shubin Liu, Mingsheng Zhong, Zhangming Zhu:
A 737nA Always-On MEMS Gyroscope with 5.45ms Start-up Time Using Burst Mode PLL Technique. 1-2 - Pieter Harpe:
Energy Efficient ADC Design Techniques. 1-2 - Jeongwon Ham, Won-Jong Choi, Young-Suk Son, Sang-Gug Lee, Kyeongha Kwon:
ASIL-D and AEC-Q100 Grade 0 Compliant Automotive RC Oscillator with Farey Sequence-based Calibration. 1-2 - Yu He, Xuqiang Zhenq, Zedong Wang, Zunsong Yanq, Hua Xu, Fangxu Lv, Mingche Lai, Xinyu Liu:
An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM. 1-2 - Jiacheng Yang, Tingxu Hu, Mo Huang, Rui Paulo Martins, Yan Lu:
A 12V-to-PoL CCC-Based Easy-Scalable Multiple-Phase Hybrid Converter with Auto VCF Balancing and Inactive CF Charging. 1-2 - Kai Li, Hantao Huang, Mingqiang Huang, Chenchen Ding, Longyang Lin, Liebing Ni, Hao Yu:
A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS. 1-2 - Mengtian Yang, Yipeng Wang, Shanshan Xie, Chieh-Pu Lo, Meizhi Wang, Sirish Oruganti, Rishabh Sehgal, Jaydeep P. Kulkarni:
CILP: An Arbitrary-bit Precision All-digital Compute-in-memory Solver for Integer Linear Programming Problems. 1-2 - Tianqi Lu, Sijun Du:
A 3-Phase Resonant Current-Mode Wireless Power Receiver with Residual-Free Energy Delivery and Digital-Assisted ZVS Achieving 94.5% Efficiency. 1-2 - Kim-Hoang Nguyen, Quyet Nguyen, Quynh-Trang Nguyen, Thanh-Tung Vu, Woojin Ahn, Loan Pham-Nguyen, Hanh-Phuc Le, Minkyu Je:
A Fully Integrated Dynamic-Voltage-Scaling Stimulator IC with Miniaturized Reconfigurable Supply Modulator and Channel Drivers for Cochlear Implants. 1-2 - Jiangchao Wu, Ke Hu, Xuanlin Chen, Pui-In Mak, Rui Paulo Martins, Man Kay Law:
A 0.25pJ/Comparison, 27.3μV Input Noise Dynamic Comparator Exploiting Stacked Floating Preamplifier with Cross-Coupled Feedback Inverters in 180nm CMOS. 1-2 - Junyao Tang, Jianqiang Jiang, Lei Zhao, Xin Zhang, Kang Wei, Cheng Huang:
A Monolithic 3-Level Single-Inductor Multiple-Output Buck Converter with State-Based Non-Linear Control Capable of Handling 1A/1.5ns Transient with On-Die LC. 1-2 - Meng Wu
S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications. 1-2 - Zilong Shen, Jiaiun Tang, Haoyang Luo, Zhongyi Wu, Zongnan Wang, Xing Zhang, Xiyuan Tang, Yuan Wang:
A 181.8dB FoMs Zoom Capacitance-to-Digital Converter with kT/C Noise Cancellation and Dead Band Operation. 1-2 - Chuan-Tung Lin, Jonghyun Oh, Kevin Lee, Mingoo Seok:
STAR-SRAM: 43.06-TFLOPS/W, 1.89-TFLOPS/mm2, 400-Kb/mm2 Floating-Point SRAM-Based Digital Computing-in-Memory Macro in 28-nm CMOS. 1-2 - Hanning Chen, Yang Ni, Wenjun Huang, Mohsen Imani:
Scalable and Interpretable Brain-Inspired Hyper-Dimensional Computing Intelligence with Hardware-Software Co-Design. 1-8 - Huanyu Ge, Haikun Jia, Wei Deng, Ruichang Ma, Baoyong Chi:
A 194.9dBc/Hz FoM and 6.8-to-11.6GHz Quad-Core Dual-Mode Class-F VCO Featuring Wideband Flicker Noise Suppression. 1-2 - Jingyi Wang, Zhangcheng Huang
A 32×32 Flash LiDAR SPAD Sensor with Up-to-1kfps Motional Target Detection by Threshold-adaptive 2D Dynamic Vision. 1-2 - Huihua Li
A 96.7%-Efficient 2.5A Scalable DC-DC Converter Module with Complementary Dual-Mode Reconfigurable Hybrid Topology Achieving Always Inductor Current Reduction, Continuously Adjustable VCR Range, and Interleaving COUT Augmentation. 1-2 - Zhaoyang Zhang, Zhichao Liu, Feiran Liu, Yinhai Gao, Yuchen Ma, Yutong Zhang, An Guo, Tianzhu Xiong, Jinwu Chen, Xi Chen, Bo Wang, Yuchen Tang, Xingyu Pu, Xing Wang, Jun Yang, Xin Si:
A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. 1-2 - Haoyu Gong, Wen-Liang Zeng, Mingqiang Guo, Chi-Seng Lam, Shulin Zhao, Rui Paulo Martins, Sai-Weng Sin:
A 75dB-SNDR 10MHz-BW 2-Channel Time-Interleaved Noise-Shaping SAR ADC Directly Powered by an On-Chip DC-DC Converter. 1-2 - Jian Yang, Tailong Xu, Xi Meng, Zhenghao Li, Jun Yin, Pui-In Mak, Rui Paulo Martins, Quan Pan:
A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS. 1-2 - Yang Liu
A 73.3% Peak Efficiency Isolated DC-DC Converter with Gap-Time Modulation using Pseudo-Hysteresis Control for -12kV/μs Common-Mode Transient Immunity. 1-2 - Arian Hashemi Talkhooncheh, Azita Emami:
Holistic Co-Design of Electronics and Photonics for High-Speed Optical Interconnects in SiP and CMOS Platforms. 1-8 - Shimin Huang, Jamie C. Ye, Shahaboddin Ghajari, Alyosha C. Molnar:
A mm-Wave Blocker-Tolerant Harmonic-Resilient N-Path Mixer-First Receiver with 6.2 dB NF and 5 dBm OOB-B1dB. 1-2 - Xin Lei, Xinhao Zheng, Yiqian Nie, Xinke Huang, Kun Fu, Yukun He, Xiaoyan Gui:
A 4×4 5-6GHz CMOS Wi-Fi Transceiver Front-End for Fiber-to-the-Room with Analog Beamforming Achieving 27dBm 1024 QAM MCS11 EIRP and -45dB EVM Floor. 1-2 - Jagannaath Shiva Letchumanan, Siddhesh Gandhi, Heyu Yin, Aditya Ramkumar, Kenneth L. Shepard:
A Mechanically Flexible 32-by-32-Element Pitch-Matched Ultrasound Front-End Transceiver with Two-Stage Beamforming for 3D Imaging. 1-2 - Junhong Sun, Changgui Yang, Yuxuan Luo, Shurong Dong, Bo Zhao:
An Interference-Resilient 120-Degree-Apart Pseudo-I/Q BLE-Compliant Wake-Up Receiver Achieving -21dB SIR, -94dBm Sensitivity, and 4-D Wake-Up Signature. 1-2 - Xiaoyu Feng, Wenyu Sun, Xinyuan Lin, Shupei Fan, Huazhong Yang, Yongpan Liu:
A 28nm 1.2GHz 5.27TOPS/W Scalable Vision/Point Cloud Deep Fusion Processor with CAM-based Universal Mapping Unit for BEVFusion Applications. 1-2 - Yikan Qiu, Yufei Ma, Meng Wu
Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow. 1-2 - Hongzhi Wu, Weitao Wu, Liping Zhong, Xuxu Cheng, Yangyi Zhang, Xiongshi Luo, Dongfan Xu, Xindan Yu, Quan Pan:
A 128Gb/s PAM-4 Transmitter with Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28nm CMOS. 1-2 - Xinyu Qin, Yichen Jin, Guoxing Wang, Sai-Weng Sin, Maurits Ortmanns, Yong Lian, Liang Qi:
A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS. 1-2 - Ji Jin, Yufa Zhou, Weiwei Xu, Lin Cheng:
A 97.3%-Peak-Efficiency Always-Dual-Path Buck-Boost Converter with Single-Mode Operation and Fast Transient Responses. 1-2 - Sukbin Lim
A 38.5TOPS/W Point Cloud Neural Network Processor with Virtual Pillar and Quadtree-based Workload Management for Real-Time Outdoor BEV Detection. 1-2 - Lishuo Deng, Zhengguo Shen, Zhuo Chen, Cai Li, Junyi Qian, Yuxuan Du, Kaize Zhou, Keran Li, Ruidong Li, Tuo Li, Xiaofeng Zou, Weiwei Shan:
An Adaptive Wide-Voltage-Range Droop Detection and Protection System Assisted with Timing Error Detection in 28nm CMOS. 1-2 - Rajath Bindiganavile, Asif Wahid, Armin Tajalli:
A 29 GHz Sub-Sampling PLL with 25.6-fs-rms RJ based on a Discrete-Time Integrating PD in 45nm RF SOI. 1-2 - Xichen Sun, Jingshu Yu, Xuliang Wang, Jin Wei, Junmin Jiang, Chenchang Zhan, Yan Wang, Xiaosen Liu:
A 92%-Efficiency 0.828μs Settling Time FC5L Voltage Regulator Featuring Time-Domain Charge Balancing & Flying Capacitor Self-Switching for Wide Dynamic Range & Fast Transient Chiplet Applications. 1-2 - Zhechen Yuan, Binzhe Yuan, Yuhan Gu, Yueyang Zheng, Yunxiang He, Xuexin Wang, Chaolin Rao, Pingqiang Zhou, Jingyi Yu, Xin Lou:
A 0.59μJ/pixel High-throughput Energy-efficient Neural Volume Rendering Accelerator on FPGA. 1-2 - Ruonan Han:
The Pursuit of Practical Applications of THz CMOS Chips (Invited). 1-7 - Pengyu He, Yuanzhe Zhao, Heng Xie, Yang Wang, Shouyi Yin, Li Li, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan, Minglei Zhang:
A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADC. 1-2 - Qiao Cai, Xinzi Xu, Yanxing Suo, Guanghua Qian, Yongfu Li, Guoxing Wang, Yong Lian, Yang Zhao:
A Saturation-Free 3.6V/1.8V DM/CM Input Range 46.6mV/μs Artifacts Recovery Sensor Interface using CT Track-and-Zoom. 1-2 - Shunichi Kubo, Yuji Gendai, Satoshi Miura, Shinsuke Hara, Satoru Tanoi, Akifumi Kasarnatsu, Takeshi Yoshida, Satoshi Tanaka, Shuhei Arnakawa, Minoru Fujishlrna:
A 20Gb/s QPSK Receiver with Mixed-Signal Carrier, Timing, and Data Recovery Using 3-bit ADCs. 1-2 - Jianhong Zhou, Yijie Li
A 103.6dB-SNDR 760mVPP-Input-Range 7.8GΩ-Input-Impedance Direct-Digitization Sensor Readout with Pseudo-Differential Transconductors and Dummy DAC. 1-2 - Yatin Gilhotra, Henry Overhauser, Heyu Yin, Eric H. Pollmann, Guy Eichler, Andrew Cheng, Taesung Jung, Nanyu Zeng, Luca P. Carloni, Kenneth L. Shepard:
A Wireless Subdural Optical Cortical Interface Device with 768 Co-Packaged Micro-LEDs for Fluorescence Imaging and Optogenetic Stimulation. 1-2 - Jinchen Wang, Isaac B. Harris, Xibi Chen, Dirk R. Englund, Ruonan Han:
A CMOS-Integrated Color Center Pulse-Sequence Control and Detection System. 1-2 - Bo Zhang, Seunghyun Moon, Mingoo Seok:
A 1-TFLOPS/W, 28-nm Deep Neural Network Accelerator Featuring Online Compression and Decompression and BF16 Digital In-Memory-Computing Hardware. 1-2 - Shan Zhang, Lingxin Meng, Zhaonan Lu, Wanyuan Qu, Shuang Song
An 871nW 96.2dB-SNDR Pipelined NS SAR ADC Achieving 180.8dB-FoMSNDR with a Charge-Efficient CLS-Assisted Two-Stage FIA. 1-2 - Quentin Schmidt
A 7.4μW and 860μm2per Channel Cryo-CMOS IC for 70-Channel Frequency-Multiplexed μs-Readout of Semiconductor Qubits. 1-2 - Zihao Tang, Mo Huang, Rui Paulo Martins, Yan Lu:
An Emulated Peak/Valley Curve Assisted Fast-Transient Buck Converter Achieving Precise One-Cycle Charge Balance with One-Parameter Calibration. 1-2 - Mahdi Parvizi, Toshi Omori, Bahar Jalali, John Rogers, Li Chen, Long Chen, Ricardo Aroca:
A 11 pA/√Hz TIA with +15dB input OMA Range for 112Gb/s PAM4 Optical Links in 22nm FDSOI. 1-2 - Weisen Zeng, Li Gao, Hui-Yang Li, Jin-Xu Xu
A Tri-Mode Filtering Power Amplifier for 5G Millimeter-Wave Dual-Side LO Injection Systems with Power-Efficiency Enhancement. 1-2 - Cheng-En Wei, Shih-Che Kuo, Chia-Hung Chen:
A 99.4 dB SFDR 91.9 dB DR Continuous-Time Incremental Delta-Sigma ADC with a Noise-Shaping SAR Quantizer and a Passive Input Feedforward Stabilization Path. 1-2 - Xin Qiao, Jiahao Song, Youming Yang
MixCIM: A Hybrid-Cell-Based Computing-in-Memory Macro with Less-Data-Movement and Activation-Memory-Reuse for Depthwise Separable Neural Networks. 1-2 - Chang Yao, Zhen Lu, Liheng Liu, Yaohua Pan, Wenhui Qin, Shaoyu Ma, Yun Sheng, Zhiliang Hong, Jiawei Xu:
A 44μW 140dB-DR Hybrid Light-to-Digital Converter with Current-Tracking Dynamic Zoom and Power-Scaling OTA. 1-2 - Guangshu Zhao, Chao Xie, Chenxi Wang, Yang Jiang, Milin Zhang, Pui-In Mak, Rui Paulo Martins, Man-Kay Law:
A 63ns Flipping Time, 93.6% Voltage Flipping Efficiency Auto-Calibrated Ultrasonic Energy Harvesting Interface from -25 to 85°C. 1-2 - Meng Yang, Changwenquan Song, Liang Wu:
A 334-to-348-GHz 7×2 Radiator Array with Coupled-Line-Based Mode-Decoupling Harmonic Enhancement and Chip-to-Waveguide Interface Achieving 30-dBm EIRP. 1-2 - Xinyu Shen, Zhao Zhang, Yong Chen, Yixi Li, Yidan Zhang, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu:
A 0.144 mm212.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMs Jitter, -271.5dB FoMN, and Sub-10% Jitter Variation. 1-2 - Li Wang
A 20-24-GHz DPSSPLL with Charge-Domain Bandwidth Optimization Scheme Achieving 61.3-fs RMS Jitter and -253-dB FoMJitter. 1-2 - Hong-Hyun Bae, Jeong-Hyun Cho, Kihyun Kim, Seunghwa Shin, Doojin Jang, Jun-Hyeok Yang, Hyun-Sik Kim:
A 7V/μs-DVS Class-G Digital-Shunt-Aided Buck Voltage Regulator Achieving a 7% Dynamic-Efficiency Drop at a 600kHz DVS Occurrence Frequency in 28nm CMOS. 1-2 - Zheyi Li, Laurent Berti, Qiuyang Lin, Jinghao Zhao
An 80MS/s 70.79dB-SNDR 60.7fJ/Conv-Step Radiation-Tolerant Semi-Time-interleaved Pipelined-SAR ADC. 1-2 - Xiangyu Mao
A Quad-Output Hybrid Buck Converter with 8-Inductor Helping One Spot from All Quarters for Multi-Core XPUs. 1-2 - Aditi Jain, Eric Fogleman, Paul Botros, Ritwik Vatsyayan, Corentin Pochet, Andrew M. Bourhis, Zhaoyi Liu, Suhas Chethan, Hanh-Phuc Le, Ian Galton, Shadi A. Dayeh, Drew A. Hall:
A 2.5-20kSps in-Pixel Direct Digitization Front-End for ECoG with In-Stimulation Recording. 1-2 - Jinbo Chen, Hui Wu, Razieh Eskandari
A Neuron-Inspired 0.0032mm2-1.38μW/Ch Wireless Implantable Neural Interface with Direct Multiplexing Front-End and Event-Driven Spike Detection and Transmission. 1-2 - Sangsu Jeong, Juyoung Oh, Dongsuk Jeon:
A 28nm 157TOPS/W 446.9Kb/mm2 Compute-In-Memory SRAM Macro with Analog-Digital Hybrid Computing for Deep Neural Network Inference. 1-2 - Mahsa Shoaran, Uisub Shin, Mohammad Ali Shaeri:
Intelligent Neural Interfaces: An Emerging Era in Neurotechnology. 1-7 - Jeongyoon Wie
A 3.3-to-11V-Supply-Range 10μW/Ch Arbitrary-Waveform-Capable Neural Stimulator with Output-Adaptive-Self-Bias and Supply-Tracking Schemes in 0.18μm Standard CMOS. 1-2 - Changxuan Han, Xun Luo:
A -10.1dBm IIP3, 0.3-40GHz Receiver Using Hybrid-Path Band-Selection with Reduced LO Coverage Bandwidth Supporting 480Mb/s 4096-QAM and 7.2Gb/s 64-QAM Modulation. 1-2 - Hongzhuo Liu, Wei Deng, Haikun Jia, Baoyong Chi:
An 11.1-to-14.9GHz Digital-Integral Hybrid-Proportional Fractional-N PLL with an LC DTC Achieving 0.52μs Locking Time and 41.3f5 Jitter. 1-2 - Jing Jin, Yuekang Guo, Meng Xu, Xiaoming Liu, Nan Sun, Jianjun Zhou:
A 470μW 20kHz-BW 107.3dB-SNDR Nested CT DSM Employing Negative-R-Based Cross-RC Filter and Weighted Multi-Threshold MSB-Pass Quantizer. 1-2 - Xiayu Wang, Zhaoyang Zhou, Chunlin Li, Jin Hu, Dong Li, Rui Ma, Yang Liu, Zhangming Zhu:
A 7.9 ps Resolution, Multi-Event TDC Using an Ultra-Low Static Phase Error DLL and High Linearity Time Amplifier for dToF Sensors. 1-2
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