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ICCAD 2007: San Jose, California, USA
- Georges G. E. Gielen:
2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007. IEEE Computer Society 2007, ISBN 1-4244-1382-6
Advances in parasitic extraction and variability modeling
- Houle Gan, Dan Jiao:
A fast and high-capacity electromagnetic solution for highspeed IC design. 1-6 - Yang Yi, Peng Li, Vivek Sarin, Weiping Shi:
Impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element method. 7-10 - Arun V. Sathanur, Ritochit Chakraborty, Vikram Jandhyala:
Statistical analysis of RF circuits using combined circuit simulator-full wave field solver approach. 11-17
Networks-on-Chip and latency-insensitive systems
- Zhonghai Lu, Axel Jantsch:
Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip. 18-25 - Mohammad Abdullah Al Faruque
, Thomas Ebi, Jörg Henkel:
Run-time adaptive on-chip communication scheme. 26-31 - Cheng-Hong Li, Luca P. Carloni
Using functional independence conditions to optimize the performance of latency-insensitive systems. 32-39
Power grid analysis
- Imad A. Ferzli, Farid N. Najm, Lars Kruse:
A geometric approach for early power grid verification using current constraints. 40-47 - Ning Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong:
Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks. 48-53 - Kai Sun, Quming Zhou, Kartik Mohanram, Danny C. Sorensen:
Parallel domain decomposition for simulation of large-scale power grids. 54-59
Synthesis and verification of quantum circuits
- Robert Wille
Fast exact Toffoli network synthesis of reversible logic. 60-64 - Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani
A novel synthesis algorithm for reversible circuits. 65-68 - George F. Viamontes, Igor L. Markov, John P. Hayes:
Checking equivalence of quantum circuits and states. 69-74
Connecting physical challenges and design approaches
- Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea I. Ismail:
A self-adjusting clock tree architecture to cope with temperature variations. 75-82 - Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu
Exploiting STI stress for performance. 83-90 - Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Automating post-silicon debugging and repair. 91-98 - Xiaoping Tang, Xin Yuan, Michael S. Gray:
Practical method for obtaining a feasible integer solution in hierarchical layout optimization. 99-104
Analytical techniques for physical optimization
- Vishal Khandelwal, Ankur Srivastava
Monte-Carlo driven stochastic optimization framework for handling fabrication variability. 105-110 - Jia Wang, Debasish Das, Hai Zhou:
Gate sizing by Lagrangian relaxation revisited. 111-118 - I-Jye Lin, Yao-Wen Chang
An efficient algorithm for statistical circuit optimization using Lagrangian relaxation. 119-124 - Shiyan Hu, Jiang Hu:
Unified adaptivity optimization of clock and logic signals. 125-130
Logic synthesis
- Soheil Ghiasi:
Incremental component implementation selection: enabling ECO in compositional system synthesis. 131-134 - Miroslav N. Velev
Exploiting hierarchy and structure to efficiently solve graph coloring as SAT. 135-142 - Sivaram Gopalakrishnan, Priyank Kalla, M. Brandon Meredith, Florian Enescu:
Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors. 143-148 - Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes:
Enhancing design robustness with reliability-aware resynthesis and logic simulation. 149-154
Memory optimization and system-level timing
- Mahmut T. Kandemir:
Data locality enhancement for CMPs. 155-159 - Ilie I. Luican, Hongwei Zhu, Florin Balasa:
Mapping model with inter-array memory sharing for multidimensional signal processing. 160-165 - Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Increasing data-bandwidth to instruction-set extensions through register clustering. 166-171 - Philip Brisk
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. 172-179 - Peggy B. McGee, Steven M. Nowick:
An efficient algorithm for time separation of events in concurrent systems. 180-187
Resilient and regular circuits
- Yu Hu, Satyaki Das, Steven Trimberger, Lei He:
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates. 188-193 - Yan Lin, Lei He:
Device and architecture concurrent optimization for FPGA transient soft error rate. 194-198 - Georgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy, Chaitali Chakrabarti:
Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering. 199-204
3-D integration challenges
- Mohit Pathak, Sung Kyu Lim
Thermal-aware Steiner routing for 3D stacked ICs. 205-211 - Roshan Weerasekera
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. 212-219 - Cesare Ferri, Sherief Reda, R. Iris Bahar
Strategies for improving the parametric yield and profits of 3D ICs. 220-226
Applications of SAT and QBF
- Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang Huang, Alan Mishchenko:
Scalable exploration of functional dependency by interpolation and incremental SAT solving. 227-233 - Kuo-Hua Wang, Chung-Ming Chan:
Incremental learning approach and SAT model for Boolean matching with don't cares. 234-239 - Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Exon Smith:
A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. 240-245
Physical synthesis comes of age
- Charles J. Alpert, Chris C. N. Chu, Paul G. Villarrubia:
The coming of age of physical synthesis. 246-249
High quality test cases for verification
- Charles H.-P. Wen
An incremental learning framework for estimating signal controllability in unit-level verification. 250-257 - Nathan Kitchen, Andreas Kuehlmann:
Stimulus generation for constrained random simulation. 258-265 - Afshin Abdollahi:
Probabilistic decision diagrams for exact probabilistic analysis. 266-272 - Tobias Nopper, Christoph Scholl, Bernd Becker
Computation of minimal counterexamples by using black box techniques and symbolic methods. 273-280
Advances in embedded systems
- Sushu Zhang, Karam S. Chatha:
Approximation algorithm for the temperature-aware scheduling problem. 281-288 - Jian-Jia Chen
Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems. 289-294 - Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, Darrel Eric Johnson, Zheng Xu:
The FAST methodology for high-speed SoC/computer simulation. 295-302 - Marco D. Santambrogio
A novel SoC design methodology combining adaptive software and reconfigurable hardware. 303-308
Can nano-photonic silicon circuits become an intra-chip interconnect technology?
- Eli Yablonovitch:
Can nano-photonic silicon circuits become an INTRA-chip interconnect technology? 309
Scaling formal verification
- Chao Wang, Hyondeuk Kim, Aarti Gupta
Hybrid CEGAR: combining variable hiding and predicate abstraction. 310-317 - Sudipta Kundu, Sorin Lerner, Rajesh Gupta:
Automated refinement checking of concurrent systems. 318-325 - Jie-Hong Roland Jiang, Wei-Lun Hung:
Inductive equivalence checking under retiming and resynthesis. 326-333
Advances in statistical timing analysis and optimization
- Ruilin Wang, Cheng-Kok Koh:
A frequency-domain technique for statistical timing analysis of clock meshes. 334-339 - Hushrav Mogal, Haifeng Qian
Clustering based pruning for statistical criticality computation under process variations. 340-343 - Ruiming Chen, Hai Zhou:
Timing budgeting under arbitrary process variations. 344-349
Sequential synthesis and FPGA mapping
- Yu Hu, Victor Shih, Rupak Majumdar, Lei He:
Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping. 350-353 - Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert K. Brayton:
Combinational and sequential mapping with priority cuts. 354-361 - Dmitry Bufistov, Jordi Cortadella
A general model for performance optimization of sequential systems. 362-369 - Lei Cheng, Deming Chen, Martin D. F. Wong
Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. 370-375
Advances in routing and clock design
- Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang:
Skew aware polarity assignment in clock tree. 376-379 - Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Li, Yao-Wen Chang
Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction. 380-385 - Fan Mo, Robert K. Brayton:
A simultaneous bus orientation and bused pin flipping algorithm. 386-389 - Hui Kong, Tan Yan, Martin D. F. Wong
Optimal bus sequencing for escape routing in dense PCBs. 390-395 - Tan Yan, Martin D. F. Wong
Untangling twisted nets for bus routing. 396-400
Improving delay test generation and performance predictors
- Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia
Low-overhead design technique for calibration of maximum frequency at multiple operating points. 401-404 - Vikram Iyengar, Jinjun Xiong
Variation-aware performance verification using at-speed structural test and statistical timing. 405-412 - Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo:
Estimation of delay test quality and its application to test generation. 413-417 - Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara:
Efficient path delay test generation based on stuck-at test generation using checker circuitry. 418-423
High level synthesis
- Jongyoon Jung, Taewhan Kim:
Timing variation-aware high-level synthesis. 424-428 - Min Ni, Seda Ogrenci Memik:
Early planning for clock skew scheduling during register binding. 429-434 - Taemin Kim, Xun Liu:
Compatibility path based binding algorithm for interconnect reduction in high level synthesis. 435-441 - Girish Venkataramani, Seth Copen Goldstein:
Operation chaining asynchronous pipelined circuits. 442-449
Analog circuit optimization
- Xin Li, Brian Taylor, YuTsun Chien, Lawrence T. Pileggi:
Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization. 450-457 - Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Sensitivity analysis for oscillators. 458-463 - Guo Yu, Peng Li:
Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling. 464-469 - Jintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong Ken Yang:
Device-circuit co-optimization for mixed-mode circuit design via geometric programming. 470-475 - Cheng Zhuo, Huafeng Zhang, Rupak Samanta, Jiang Hu, Kangsheng Chen:
Modeling, optimization and control of rotary traveling-wave oscillator. 476-480
Global routing
- Subarna Sinha, Charles C. Chiang:
A methodology for fast and accurate yield factor estimation during global routing. 481-487 - Muhammet Mustafa Ozdal, Martin D. F. Wong
Archer: a history-driven global routing algorithm. 488-495 - Jarrod A. Roy, Igor L. Markov:
High-performance routing at the nanometer scale. 496-502 - Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan:
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router. 503-508
Test compression and test power
- Hao Fang, Chenguang Tong, Bo Yao, Xiaodi Song, Xu Cheng:
CacheCompress: a novel approach for test data compression with cache for IP embedded cores. 509-512 - Mango Chia-Tso Chao, Kwang-Ting Cheng
A hybrid scheme for compacting test responses with unknown values. 513-519 - Chia-Yi Lin, Hung-Ming Chen:
A selective pattern-compression scheme for power and test-data reduction. 520-525 - Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji:
Methodology for low power test pattern generation using activity threshold control logic. 526-529
Gate level physical synthesis
- Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang
ECO timing optimization using spare cells. 530-535 - Jürgen Werber, Dieter Rautenbach, Christian Szegedy:
Timing optimization by restructuring long combinatorial paths. 536-543 - Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Engineering change using spare cells with constant insertion. 544-547 - Lin Yuan, Gang Qu:
Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization. 548-551
Interconnect modeling and optimization
- Byungsub Kim, Vladimir Stojanovic:
Equalized interconnects for on-chip networks: modeling and optimization framework. 552-559 - Deepak C. Sekar, Azad Naeemi
IntSim: A CAD tool for optimization of multilevel interconnect networks. 560-567 - Hong Li, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan
A fast band-matching technique for interconnect inductance modeling. 568-571
Formal verification at higher levels of abstraction
- Daniel Kroening
Formal verification at higher levels of abstraction. 572-578
Floorplanning
- Qiang Ma, Evangeline F. Y. Young, Kong-Pang Pun:
Analog placement with common centroid constraints. 579-585 - Chunta Chu, Xinyi Zhang, Lei He, Tong Jing:
Temperature aware microprocessor floorplanning considering application dependent power load. 586-589 - Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou:
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. 590-597
System-level synthesis and interconnect design
- Feng Wang, Chrysostomos Nicopoulos
Variation-aware task allocation and scheduling for MPSoC. 598-603 - Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin:
A design flow dedicated to multi-mode architectures for DSP applications. 604-611 - Yi Wang, Dan Zhao:
The design and synthesis of a synchronous and distributed MAC protocol for wireless network-on-chip. 612-617 - Madhu Mutyam
Selective shielding: a crosstalk-free bus encoding technique. 618-621
Advances in model order reduction techniques for interconnect analysis
- Natalie Nakhla, Michel S. Nakhla, Ramachandra Achar:
Sparse and passive reduction of massively coupled large multiport interconnects. 622-626 - Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu:
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. 627-631 - Alexander V. Mitev, Michael M. Marefat, Dongsheng Ma, Janet Meiling Wang:
Principle Hessian direction based parameter reduction with process variation. 632-637
Mosfet modeling for 45nm & beyond
- Yu Cao, Colin C. McAndrew:
MOSFET modeling for 45nm and beyond. 638-643
Voltage assignment in floorplanning
- Qiang Ma, Evangeline F. Y. Young:
Voltage island-driven floorplanning. 644-649 - Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang:
An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. 650-655 - Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar
Module assignment for pin-limited designs under the stacked-Vdd paradigm. 656-659
Variation tolerant circuits
- Gregory K. Chen, David T. Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim:
Yield-driven near-threshold SRAM design. 660-666 - Vivek Joshi, David T. Blaauw, Dennis Sylvester:
Soft-edge flip-flops for improved timing yield: design and optimization. 667-673 - Yousra Alkabani, Farinaz Koushanfar
Remote activation of ICs for piracy prevention and digital right management. 674-677
Advanced models for static timing analysis
- Chandramouli V. Kashyap, Chirayu S. Amin, Noel Menezes, Eli Chiprout:
A nonlinear cell macromodel for digital applications. 678-685 - Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail:
Including inductance in static timing analysis. 686-691 - Alexander V. Mitev, Dinesh Ganesan, Dheepan Shanmugasundaram, Yu Cao, Janet Meiling Wang:
A robust finite-point based gate model considering process variations. 692-697 - Ravikishore Gandikota, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada:
Victim alignment in crosstalk aware timing analysis. 698-704
Variation aware timing verification
- Vladimir Zolotov, Jinjun Xiong
Compact modeling of variational waveforms. 705-712 - Frank Huebbers, Ali Dasdan, Yehea I. Ismail:
Multi-layer interconnect performance corners for variation-aware timing analysis. 713-718 - Frank Liu:
An efficient method for statistical circuit simulation. 719-724 - Zhuo Feng, Peng Li:
A methodology for timing model characterization for statistical static timing analysis. 725-729
Reliability driven modeling and analysis for deep submicron technologies
- Kunhyuk Kang, Sang Phill Park, Kaushik Roy, Muhammad Ashraful Alam:
Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance. 730-734 - Wenping Wang, Zile Wei, Shengqi Yang, Yu Cao:
An efficient method to identify critical gates under circuit aging. 735-740 - Kanak Agarwal, Frank Liu:
Efficient computation of current flow in signal wires for reliability analysis. 741-746 - Jung Hwan Choi, Jayathi Murthy, Kaushik Roy:
The effect of process variation on device temperature in FinFET circuits. 747-751
Design automation and defect tolerance techniques for emerging technologies
- Ping-Hung Yuh, Chia-Lin Yang
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. 752-757 - Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei Wang:
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture. 758-764 - M. Haykel Ben Jamaa, Kirsten E. Moselund
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays. 765-772 - Susmit Biswas, Gang Wang, Tzvetan S. Metodi, Ryan Kastner
Combining static and dynamic defect-tolerance techniques for nanoscale memory systems. 773-778
Leakage power reduction
- Yu-Ting Chen, Da-Cheng Juan, Ming-Chao Lee, Shih-Chieh Chang:
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon. 779-782 - Aida Todri
Analysis and optimization of power-gated ICs with multiple power gating configurations. 783-790 - Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram:
Sizing and placement of charge recycling transistors in MTCMOS circuits. 791-796 - Jaehyun Kim, Youngsoo Shin:
Minimizing leakage power in sequential circuits by using mixed Vt flip-flops. 797-802
Power modeling and optimization
- Yiyu Shi, Jinjun Xiong
Efficient decoupling capacitance budgeting considering operation and process variations. 803-810 - Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs. 811-816 - Yuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao:
A novel technique for incremental analysis of on-chip power distribution networks. 817-823 - Xiaoyao Liang, Kerem Turgay, David M. Brooks:
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques. 824-830
Improving planarity and patterning
- Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang
Novel wire density driven full-chip routing for CMP variation control. 831-838 - Jingyu Xu, Subarna Sinha, Charles C. Chiang:
Accurate detection for process-hotspots with vias and incomplete specification. 839-846 - Peng Yu, David Z. Pan:
TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction. 847-853 - Peng Yu, David Z. Pan:
A novel intensity based optical proximity correction algorithm with speedup in lithography simulation. 854-859
Model order reduction for parameterized and non-linear systems
- Bradley N. Bond, Luca Daniel:
Stabilizing schemes for piecewise-linear reduced order models via projection and weighting functions. 860-866 - Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng:
Parameterized model order reduction via a two-directional Arnoldi process. 868-873 - Wei Dong, Zhuo Feng, Peng Li:
Efficient VCO phase macromodel generation considering statistical parametric variations. 874-878 - Kin Cheong Sou
Bounding L2 gain system error generated by approximations of the nonlinear vector field. 879-886 - Jaeha Kim, Kevin D. Jones
Variable domain transformation for linear PAC analysis of mixed-signal systems. 887-894
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