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ICCAD 2009: San Jose, California, USA
- Jaijeet S. Roychowdhury:
2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009. ACM 2009, ISBN 978-1-60558-800-1
Functional Verification
- Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips, Claudio Pinello, Radu Zlatanovici:
First steps towards SAT-based formal analog verification. 1-8 - Chih-Jen Hsu, Shao-Lun Huang, Chi-An Wu, Chung-Yang Huang:
Interpolant generation without constructing resolution graph. 9-12 - Roberto Bruttomesso, Natasha Sharygina
:
A scalable decision procedure for fixed-width bit-vectors. 13-20
Advances in Routing
- Liang Li, Zaichen Qian, Evangeline F. Y. Young:
Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree. 21-25 - Chih-Hung Liu, Shih-Yi Yuan, Sy-Yen Kuo, Jung-Hung Weng:
Obstacle-avoiding rectilinear Steiner tree construction based on Steiner point selection. 26-32 - Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak:
How to consider shorts and guarantee yield rate improvement for redundant wire insertion. 33-38 - Tsun-Ming Tseng
Power-switch routing for coarse-grain MTCMOS technologies. 39-46
Scheduling Techniques for Low Power
- Jason Cong, Bin Liu, Zhiru Zhang
Scheduling with soft constraints. 47-54 - Muhammad Shafique, Lars Bauer, Jörg Henkel:
REMiS: Run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set. 55-62 - Baoxian Zhao, Hakan Aydin, Dakai Zhu:
Enhanced reliability-aware power management through shared recovery technique. 63-70
Resilient Computing
- James W. Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik:
Resilient circuits - Enabling energy-efficient performance and reliability. 71-73 - Kishor S. Trivedi, Dong Seong Kim
Resilience in computer systems and networks. 74-77
Advances in Test Efficiency
- Mingjing Chen, Alex Orailoglu:
Scan power reduction in linear test data compression scheme. 78-82 - Nuno Alves, Jennifer Dworak, R. Iris Bahar
Compacting test vector sets via strategic use of implications. 83-88 - Jiniun Xionq, Yiyu Shi, Vladimir Zolotov, Chandu Visweswariah:
Pre-ATPG path selection for near optimal post-ATPG process space coverage. 89-96 - Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara:
A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. 97-104
Advances in FPGA Synthesis and Trustable
- Zhe Feng, Yu Hu, Lei He, Rupak Majumdar:
IPR: In-Place Reconfiguration for FPGA fault tolerance. 105-108 - Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia
A circuit-software co-design approach for improving EDP in reconfigurable frameworks. 109-112 - Rajat Subhra Chakraborty, Swarup Bhunia
Security against hardware Trojan through a novel application of design obfuscation. 113-116 - Lang Lin, Wayne P. Burleson, Christof Paar:
MOLES: Malicious off-chip leakage enabled by side-channels. 117-122 - Yousra Alkabani, Farinaz Koushanfar
Consistency-based characterization for IC Trojan detection. 123-127
Design Automation for Biological Systems
- Noah Ollikainen, Ellen Sentovich, Carlos Coelho, Andreas Kuehlmann, Tanja Kortemme:
SAT-based protein design. 128-135 - Adam Shea, Marc D. Riedel, Brian Fett, Keshab K. Parhi:
Synthesizing sequential register-based computation with biochemistry. 136-143 - Ehsan Ullah, Kyongbum Lee, Soha Hassoun:
An algorithm for identifying dominant-edge metabolic pathways. 144-150 - Tsung-Wei Huang, Chun-Hsien Lin, Tsung-Yi Ho
A contamination aware droplet routing algorithm for digital microfluidic biochips. 151-156
Analysis and Mitigation of Transient and Permanent Failures
- Huan-Kai Peng, Charles H.-P. Wen, Jayanta Bhadra:
On soft error rate analysis of scaled CMOS designs - A statistical perspective. 157-163 - Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie:
Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning. 164-171 - Lu Wan, Deming Chen:
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior. 172-179 - Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
A variation-aware preferential design approach for memory based reconfigurable computing. 180-183
Emerging Topics in Test and Reliability
- Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim
Pre-bond testable low-power clock tree design for 3D stacked ICs. 184-190 - Li Jiang, Qiang Xu
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint. 191-196 - Tzuo-Fan Chien, Wen-Chi Chao, James Chien-Mo Li, Yao-Wen Chang, Kuan-Yu Liao, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng:
BIST design optimization for large-scale embedded memory cores. 197-200 - Yanjing Li, Onur Mutlu, Subhasish Mitra:
Operating system scheduling for efficient online self-test in robust systems. 201-208
Timing Closure and Design Robustness
- Khaled R. Heloue, Chandramouli V. Kashyap, Farid N. Najm:
Quantifying robustness metrics in parameterized static timing analysis. 209-216 - Sari Onaissi, Khaled R. Heloue, Farid N. Najm:
PSTA-based branch and bound approach to the silicon speedpath isolation problem. 217-224 - Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler:
Timing Arc based logic analysis for false noise reduction. 225-230
Routing in Alternative Technologies
- Muhammet Mustafa Ozdal, Renato Fernandes Hentschke:
Exact route matching algorithms for analog and mixed signal integrated circuits. 231-238 - Po-Wei Lee, Chung-Wei Lin, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng:
An efficient pre-assignment routing algorithm for flip-chip designs. 239-244 - Tan Yan, Hui Kong, Martin D. F. Wong
Optimal layer assignment for escape routing of buses. 245-248 - Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang:
Pad assignment for die-stacking System-in-Package design. 249-255
Emerging Design and Memory Technologies
- Hitoshi Mizunuma, Chia-Lin Yang, Yi-Chang Lu
Thermal modeling for 3D-ICs with integrated microchannel cooling. 256-263 - Ping Zhou
Energy reduction for STT-RAM using early write termination. 264-268 - Xiangyu Dong, Norman P. Jouppi, Yuan Xie:
PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM. 269-275
Tutorial
- John F. Croix, Sunil P. Khatri:
Introduction to GPU programming for EDA. 276-280
Analytical Advances in Physical Synthesis
- Yujia Feng, Shiyan Hu:
The epsilon-approximation to discrete VT assignment for leakage power minimization. 281-287 - Tony F. Chan, Jason Cong, Eric Radke:
A rigorous framework for convergent net weighting schemes in timing-driven placement. 288-294 - Zuochang Ye, Zhiping Yu:
An efficient algorithm for modeling spatially-correlated process variation in statistical full-chip leakage analysis. 295-301
Thermal-Aware Management Techniques for Multi-Core Architectures
- Thomas Ebi, Mohammad Abdullah Al Faruque, Jörg Henkel:
TAPE: Thermal-aware agent-based power econom multi/many-core architectures. 302-309 - Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha:
Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. 310-313 - Ramkumar Jayaseelan, Tulika Mitra:
A hybrid local-global approach for multi-core thermal management. 314-320
Statistical Timing Analysis and Its Application
- Jaeyong Chung, Jacob A. Abraham:
A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTA. 321-327 - Min Gong, Hai Zhou, Jun Tao, Xuan Zeng:
Binning optimization based on SSTA for transparently-latched circuits. 328-335 - Bing Li, Ning Chen, Ulf Schlichtmann
Timing model extraction for sequential circuits considering process variations. 333-343
Congestion Driven Placement
- Yanheng Zhang, Chris Chu:
CROP: Fast and effective congestion refinement of placement. 344-350 - Ke-Ren Dai, Chien-Hung Lu, Yih-Lang Li:
GRPlacer: Improving routability and wire-length of global routing with circuit replacement. 351-356 - Jarrod A. Roy, Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov:
CRISP: Congestion reduction by iterated spreading during placement. 357-362 - Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan:
A study of routability estimation and clustering in placement. 363-366
New Applications in Logic Synthesis
- Weikang Qian, Marc D. Riedel
The synthesis of combinational logic to generate probabilities. 367-374 - Seonggwan Lee, Seungwhun Paik, Youngsoo Shin:
Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits. 375-380 - ShengYu Shen, Jianmin Zhang, Ying Qin, Sikun Li:
Synthesizing complementary circuits automatically. 381-388
Advanced Modeling and Simulation Methods
- Chenjie Gu:
QLMOR: A new projection-based approach for nonlinear model order reduction. 389-396 - Onder Suvak, Alper Demir:
Computing quadratic approximations for the isochrons of oscillators: A general theory and advanced numerical methods. 397-402 - Wei Dong, Peng Li:
Final-value ODEs: Stable numerical integration and its application to parallel circuit analysis. 403-409 - Heidi Thornquist, Eric R. Keiter
A parallel preconditioning strategy for efficient transistor-level circuit simulation. 410-417
Characterization and Compensation of Variability
- Kanak Agarwal, Dhruva Acharyya, Jim Plusquellic:
Characterizing within-die variation from multiple supply port IDDQ measurements. 418-424 - Vladimir Zolotov, Chandu Visweswariah, Jinjun Xiong
Voltage binning under process variation. 425-432 - Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton:
Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits. 433-440 - Cheng Zhuo, David T. Blaauw, Dennis Sylvester:
Post-fabrication measurement-driven oxide breakdown reliability prediction and management. 441-448
Policies and Methods for Low Power
- Baoxian Zhao, Hakan Aydin:
Minimizing expected energy consumption through optimal integration of DVS and DPM. 449-456 - Ming-Chao Lee, Yu-Ting Chen, Yo-Tzu Cheng, Shih-Chieh Chang:
An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs. 457-460 - Ying Tan, Wei Liu, Qinru Qiu:
Adaptive power management using reinforcement learning. 461-467 - Hao Xu, Ranga Vemuri
Temporal and spatial idleness exploitation for optimal-grained leakage control. 468-473
Emerging Memory Technologies
- Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay:
A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies. 474-477 - Soogine Chong, Kerem Akarvardar, Roozbeh Parsa, Jun-Bo Yoon, Roger T. Howe, Subhasish Mitra, H.-S. Philip Wong
Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage. 478-484 - Yenpo Ho, Garng M. Huang, Peng Li:
Nonvolatile memristor memory: Device characteristics and design implications. 485-490 - Yong Zhang, Peng Li:
Gene-regulatory memories: Electrical-equivalent modeling, simulation and parameter identification. 491-496
Advanced Device Reliability and Modeling
- Rouwaida Kanj, Rajiv V. Joshi, Chad Adams, James D. Warnock, Sani R. Nassif:
An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects. 497-504 - Seid Hadi Rasouli, Kazuhiko Endo
Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization. 505-512 - Chi-Chao Wang, Wei Zhao, Frank Liu, Min Chen, Yu Cao:
Modeling of layout-dependent stress effect in CMOS design. 513-520 - Jiying Xue, Zuochang Ye, Yangdong Deng, Hongrui Wang, Liu Yang, Zhiping Yu:
Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimization. 521-528
Clock Optimization and Parallel Algorithm in EDA
- Xiaoji Ye, Srinath Narasimhan, Peng Li:
Leveraging efficient parallel pattern search for clock mesh optimization. 529-534 - Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang:
Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. 535-538 - Yangdong Deng, Bo D. Wang, Shuai Mu:
Taming irregular EDA applications on GPUs. 539-546 - Jonas Casanova, Jordi Cortadella
Multi-level clustering for clock skew optimization. 547-554
Analysis and Optimization of Network-On-Chip and Multiprocessor SOC
- Yue Qian, Zhonghai Lu, Wenhua Dou:
From 2D to 3D NoCs: A case study on worst-case communication performance. 555-562 - Ming-che Lai, Lei Gao, Nong Xiao, Zhiying Wang:
An accurate and efficient performance analysis approach based on queuing model for network on chip. 563-570 - Nikita Nikitin, Jordi Cortadella
A performance analytical model for Network-on-Chip with constant service time routers. 571-578 - Dara Rahmati
A method for calculating hard QoS guarantees for Networks-on-Chip. 579-586 - Jerónimo Castrillón, Diandian Zhang, Torsten Kempf, Bart Vanthournout, Rainer Leupers, Gerd Ascheid:
Task management in MPSoCs: An ASIP approach. 587-594
Design-Patterning Interactions
- Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif:
Simultaneous layout migration and decomposition for double patterning technology. 595-600 - Yue Xu, Chris Chu:
GREMA: Graph reduction based efficient mask assignment for double patterning technology. 601-606 - Mohit Gupta, Kwangok Jeong, Andrew B. Kahng:
Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography. 607-614 - Rani S. Ghaida, Puneet Gupta
A framework for early and systematic evaluation of design rules. 615-622
Yield Estimation and Optimization for SRAMs
- Javid Jaffari, Mohab Anis:
Adaptive sampling for efficient failure probability analysis of SRAM cells. 623-630 - Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das:
Yield estimation of SRAM circuits using "Virtual SRAM Fab". 631-636 - Ashish Kumar Singh, Ku He, Constantine Caramanis
Mitigation of intra-array SRAM variability using adaptive voltage architecture. 637-644
Thermal Modeling and Analysis at Chip and Platform Levels
- Young-Joon Lee, Rohan Goel, Sung Kyu Lim
Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs. 645-651 - Donghwa Shin, Jihun Kim, Naehyuck Chang, Jinhang Choi, Sung Woo Chung, Eui-Young Chung:
Energy-optimal dynamic thermal management for green computing. 652-657 - Chuan Xu, Lijun Jiang, Seshadri K. Kolluri, Barry J. Rubin, Alina Deutsch, Howard H. Smith, Kaustav Banerjee:
Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologies. 658-665
Analytic Placement
- Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang:
Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs. 666-673 - Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim
A study of Through-Silicon-Via impact on the 3D stacked IC layout. 674-680 - Jason Cong, Yi Zou:
Parallel multi-level analytical global placement on graphics processing units. 681-688
Performance and Power Issues in Embedded System-Level Design
- Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Memory organization and data layout for instruction set extensions with architecturally visible storage. 689-696 - Jason Cong, Wei Jiang, Bin Liu, Yi Zou:
Automatic memory partitioning and scheduling for throughput and power optimization. 697-704 - Hengyu Long, Yongpan Liu, Yiqun Wang, Robert P. Dick, Huazhong Yang:
Battery allocation for wireless sensor network lifetime maximization under cost constraints. 705-712
Biological Circuits and Systems
- Chris J. Myers, Nathan A. Barker, Hiroyuki Kuwahara, Kevin R. Jones, Curtis Madsen, Nam-Phuong D. Nguyen:
Genetic design automation. 713-716
Statistical Simulation and Optimization of Serial Link and Wordlength
- Michael J. Tsuk, Daniel Dvorscak, Chin Siong Ong, Jacob White:
An electrical-level superposed-edge approach to statistical serial link simulation. 717-724 - Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti:
Joint design-time and post-silicon optimization for digitally tuned analog circuits. 725-730 - Linsheng Zhang, Yan Zhang, Wenbiao Zhou:
Fast trade-off evaluation for digital signal processing systems during wordlength optimization. 731-738 - Bijan Alizadeh, Masahiro Fujita:
Improved heuristics for finite word-length polynomial datapath optimization. 739-744
Parasitic Extraction, Modeling, and Reduction Techniques
- Xiaoyi Wang, Yici Cai, Qiang Zhou, Sheldon X.-D. Tan, Thom Jefferson A. Eguia:
Decoupling capacitance efficient placement for reducing transient power supply noise. 745-751 - Tarek A. El-Moselhy, Ibrahim M. Elfadel, Luca Daniel:
A hierarchical floating random walk algorithm for fabric-aware 3D capacitance extraction. 752-758 - Ritochit Chakraborty, Arun V. Sathanur, Vikram Jandhyala:
Active-passive co-synthesis of multi-GigaHertz radio frequency circuits with broadband parametric macromodels of on-chip passives. 759-766 - Zheng Zhang, Chi-Un Lei
GHM: A generalized Hamiltonian method for passivity test of impedance/admittance descriptor systems. 767-773 - Zuochang Ye, Luís Miguel Silveira
Fast and reliable passivity assessment and enforcement with extended Hamiltonian pencil. 774-778
Advanced Boolean Techniques in Logic Synthesis
- Jie-Hong Roland Jiang, Hsuan-Po Lin, Wei-Lun Hung:
Interpolating functions from large Boolean relations. 779-784 - Yung-Chih Chen, Chun-Yao Wang:
Fast detection of node mergers using logic implications. 785-788 - Smita Krishnaswamy, Haoxing Ren, Nilesh Modi, Ruchir Puri:
DeltaSyn: An efficient logic difference optimizer for ECO synthesis. 789-796 - Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Iterative layering: Optimizing arithmetic circuits by structuring the information flow. 797-804
Tutorial
- Michael D. Moffitt:
Global routing revisited. 805-808
Power 7 - Verification Challenges of a High-End 8-Core Microprocessor
- Klaus-Dieter Schubert:
POWER7 - Verification challenge of a multi-core processor. 809-812
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