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34th ICCD 2016: Scottsdale, AZ, USA
- 34th IEEE International Conference on Computer Design, ICCD 2016, Scottsdale, AZ, USA, October 2-5, 2016. IEEE Computer Society 2016, ISBN 978-1-5090-5142-7
- Elliott Forbes, Eric Rotenberg:
Fast register consolidation and migration for heterogeneous multi-core processors. 1-8 - Keni Qiu, Yuanhui Ni, Weigong Zhang, Jing Wang, Xiaoqiang Wu, Chun Jason Xue, Tao Li:
An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor. 9-16 - Arjun Deb, Paolo Faraboschi
, Ali Shafiee, Naveen Muralimanohar, Rajeev Balasubramonian, Robert Schreiber:
Enabling technologies for memory compression: Metadata, mapping, and prediction. 17-24 - Kevin Hsieh
Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation. 25-32 - Itir Akgun
Scalable memory fabric for silicon interposer-based multi-core systems. 33-40 - Wei-Ting Jonas Chan, Yang Du, Andrew B. Kahng, Siddhartha Nath, Kambiz Samadi:
BEOL stack-aware routability prediction from placement using data mining techniques. 41-48 - Hasan Erdem Yantir, Mohammed E. Fouda, Ahmed M. Eltawil
Process variations-aware resistive associative processor design. 49-55 - Yisong Chang, Ke Zhang, Sally A. McKee, Lixin Zhang, Mingyu Chen, Liqiang Ren, Zhiwei Xu:
Extending On-chip Interconnects for rack-level remote resource access. 56-63 - Wenjian Xiao, Huanqing Dong, Liuying Ma, Zhenjun Liu, Qiang Zhang:
HS-BAS: A hybrid storage system based on band awareness of Shingled Write Disk. 64-71 - Yanbing Jiang, Chentao Wu, Jie Li
BDR: A Balanced Data Redistribution scheme to accelerate the scaling process of XOR-based Triple Disk Failure Tolerant arrays. 72-79 - Guojin Wu, Yuhui Deng
Using Provenance to boost the Metadata Prefetching in distributed storage systems. 80-87 - Pai-Shun Ting, John P. Hayes:
Isolation-based decorrelation of stochastic circuits. 88-95 - Yesung Kang, Jaewoo Kim, Seokhyeong Kang:
Novel approximate synthesis flow for energy-efficient FIR filter. 96-102 - Ching Zhou, Yu-Shiang Lin, Pong-Fei Lu, Bruce M. Fleischer, David J. Frank, Leland Chang:
Synthesis design strategies for energy-efficient microprocessors. 103-108 - Monther Abusultan, Sunil P. Khatri:
Implementing low power digital circuits using flash devices. 109-116 - Andreas Sembrant, Erik Hagersten, David Black-Schaffer:
Data placement across the cache hierarchy: Minimizing data movement with reuse-aware placement. 117-124 - Junghoon Lee, Taehoon Kim
Dynamic prefetcher reconfiguration for diverse memory architectures. 125-132 - Shin-Ying Lee, Carole-Jean Wu:
Ctrl-C: Instruction-Aware Control Loop Based Adaptive Cache Bypassing for GPUs. 133-140 - Rekha Govindaraj, Swaroop Ghosh:
A strong arbiter PUF using resistive RAM within 1T-1R memory architecture. 141-148 - Kelvin Ly, Orlando Arias, Jacob Wurm, Khoa Hoang, Kaveh Shamsi, Yier Jin
Voting system design pitfalls: Vulnerability analysis and exploitation of a model platform. 149-152 - Mohammad-Mahdi Bidmeshki, Gaurav Rajavendra Reddy, Liwei Zhou, Jeyavijayan Rajendran, Yiorgos Makris
Hardware-based attacks to compromise the cryptographic security of an election system. 153-156 - Nektarios Georgios Tsoutsos, Michail Maniatakos
Cryptographic vote-stealing attacks against a partially homomorphic e-voting architecture. 157-160 - Rizwana Begum, Mark Hempstead, Guru Prasad Srinivasa, Geoffrey Challen:
Algorithms for CPU and DRAM DVFS under inefficiency constraints. 161-168 - Nadja Peters, Dominik Fuss, Sangyoung Park
Frame-based and thread-based power management for mobile games on HMP platforms. 169-176 - Simon J. Hollis, Edward Ma, Radu Marculescu
nOS: A nano-sized distributed operating system for many-core embedded systems. 177-184 - Xun Jiao, Yu Jiang, Abbas Rahimi
WILD: A workload-based learning model to predict dynamic delay of functional units. 185-192 - Prabanjan Komari, Ranga Vemuri
A novel simulation based approach for trace signal selection in silicon debug. 193-200 - Venkata Yaswanth Raparti, Nishit Ashok Kapadia, Sudeep Pasricha:
CHARM: A checkpoint-based resource management framework for reliable multicore computing in the dark silicon era. 201-208 - Keni Qiu, Junpeng Luo, Zhiyao Gong, Weigong Zhang, Jing Wang, Yuanchao Xu, Tao Li, Chun Jason Xue:
Refresh-aware loop scheduling for high performance low power volatile STT-RAM. 209-216 - Meysam Taassori, Ali Shafiee, Rajeev Balasubramonian:
Understanding and alleviating intra-die and intra-DIMM parameter variation in the memory system. 217-224 - Taizhi Liu, Chang-Chih Chen, Jiadong Wu, Linda S. Milor
SRAM stability analysis for different cache configurations due to Bias Temperature Instability and Hot Carrier Injection. 225-232 - Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Blake Skinner, Jose Renau:
Fluid Pipelines: Elastic circuitry meets Out-of-Order execution. 233-240 - Xue Lin, Yuankun Xue, Paul Bogdan, Yanzhi Wang, Siddharth Garg, Massoud Pedram:
Power-aware virtual machine mapping in the data-center-on-a-chip paradigm. 241-248 - Qi Jia, Huiyang Zhou
Tuning Stencil codes in OpenCL for FPGAs. 249-256 - Amir Momeni, Hamed Tabkhi, Gunar Schirner, David R. Kaeli:
Hardware thread reordering to boost OpenCL throughput on FPGAs. 257-264 - Umair Ullah Tariq
Energy-aware scheduling of conditional task graphs with deadlines on MPSoCs. 265-272 - Satendra Kumar, Ankur Gupta
Design automation of multiple-demand mixture preparation using a K-array rotary mixer on digital microfluidic biochips. 273-280 - Caiwen Ding
Luminescent solar concentrator-based photovoltaic reconfiguration for hybrid and plug-in electric vehicles. 281-288 - Caiwen Ding
Dynamic converter reconfiguration for near-threshold non-volatile processors using in-door energy harvesting. 289-295 - Byungchul Hong, Yongkee Kwon, Jung Ho Ahn
Adaptive and flexible key-value stores through soft data partitioning. 296-303 - Majid Jalili, Hamid Sarbazi-Azad:
Tolerating more hard errors in MLC PCMs using compression. 304-311 - Mounika Ponugoti, Aleksandar Milenkovic
Exploiting cache coherence for effective on-the-fly data tracing in multicores. 312-319 - Xushen Han, Dajiang Zhou, Shihao Wang, Shinji Kimura:
CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks. 320-327 - Liang Wang, Kevin Skadron
Lumos+: Rapid, pre-RTL design space exploration on accelerator-rich heterogeneous architectures with reconfigurable logic. 328-335 - Fatemeh Aghaaliakbari, Mohaddeseh Hoveida, Mohammad Arjomand, Majid Jalili, Hamid Sarbazi-Azad:
Efficient processor allocation in a reconfigurable CMP architecture for dark silicon era. 336-343 - Majed Valad Beigi, Gokhan Memik:
TESLA: Using microfluidics to thermally stabilize 3D stacked STT-RAM caches. 344-347 - Aliyar Attaran, Hassan Salmani, Houman Homayoun, Hamid Mahmoodi
Dynamic single and Dual Rail spin transfer torque look up tables with enhanced robustness under CMOS and MTJ process variations. 348-351 - Wen Zong, Qiang Xu
DOART: A low-power and low-latency Network-on-Chip. 352-355 - Xin Shi, Fei Wu, Xidong Guan, Changsheng Xie:
Error behaviors testing with temperature and magnetism dependency for MRAM. 356-359 - Mehran Goli
AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration. 360-363 - Ping-Lin Yang, Malgorzata Marek-Sadowska:
A fast, fully verifiable, and hardware predictable ASIC design methodology. 364-367 - Lei Liu, Hao Yang, Yong Li, Mengyao Xie, Lian Li, Chenggang Wu:
Memos: A full hierarchy hybrid memory management framework. 368-371 - Wei Shu, Nian-Feng Tzeng:
Relinquishment coherence for enhancing directory efficiency in chip multiprocessors. 372-375 - Yang Liu, Hung-Wei Tseng
Hippogriff: Efficiently moving data in heterogeneous computing systems. 376-379 - Kyu Yeun Kim, Jinsu Park, Woongki Baek:
IACM: Integrated adaptive cache management for high-performance and energy-efficient GPGPU computing. 380-383 - Yang Liu, Hung-Wei Tseng
SPMario: Scale up MapReduce with I/O-Oriented Scheduling for the GPU. 384-387 - Hayato Nomura, Hiroyuki Katchi, Hidetsugu Irie, Shuichi Sakai
"Stubborn" strategy to mitigate remaining cache misses. 388-391 - Florian Huemer
A new coding scheme for fault tolerant 4-phase delay-insensitive codes. 392-395 - Tiago T. Jost, Gabriel L. Nazar, Luigi Carro:
Scalable memory architecture for soft-core processors. 396-399 - Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin, Kapil R. Dandekar
Wireless Network-on-Chip analysis of propagation technique for on-chip communication. 400-403 - Amirhossein Mirhosseini, Mohammad Sadrosadati, Maryam Zare, Hamid Sarbazi-Azad:
Quantifying the difference in resource demand among classic and modern NoC workloads. 404-407 - Yin Liu, Hariharasudhan Venkataraman, Zisheng Zhang, Keshab K. Parhi
Machine learning classifiers using stochastic logic. 408-411 - Abbas A. Fairouz, Monther Abusultan, Sunil P. Khatri:
A novel hardware hash unit design for modern microprocessors. 412-415 - Monther Abusultan, Sunil P. Khatri:
Exploring static and dynamic flash-based FPGA design topologies. 416-419 - Santiago Bock, Bruce R. Childers, Rami G. Melhem, Daniel Mossé:
Concurrent Migration of Multiple Pages in software-managed hybrid main memory. 420-423 - Arash Nejat, David Hély
How logic masking can improve path delay analysis for Hardware Trojan detection. 424-427 - Ramin Fallahzadeh, Hassan Ghasemzadeh:
CyHOP: A generic framework for real-time power-performance optimization in networked wearable motion sensors. 428-431 - Xinying Wang, Joseph Zambreno:
Parallelizing Latent Semantic Indexing using an FPGA-based architecture. 432-435 - Seil Lee, Hanjoo Kim, Seongsik Park
CloudSocket: Smart grid platform for datacenters. 436-439 - Sikhar Patranabis, Debapriya Basu Roy, Praveen Kumar Vadnala, Debdeep Mukhopadhyay, Santosh Ghosh:
Shuffling across rounds: A lightweight strategy to counter side-channel attacks. 440-443 - Cunlu Li, Dezun Dong, Xiangke Liao, Fei Lei, Ji Wu:
CCAS: Contention and congestion aware switch allocation for network-on-chips. 444-447 - Manish Rana, Ramon Canal
SRAM memory margin probability failure estimation using Gaussian Process regression. 448-451 - Steffen Peter, Tony Givargis:
Towards a timing attack aware high-level synthesis of integrated circuits. 452-455 - Xi-Yue Xiang, Saugata Ghose, Onur Mutlu, Nian-Feng Tzeng:
A model for Application Slowdown Estimation in on-chip networks and its use for improving system fairness and performance. 456-463 - Airan Shao, Dongsheng Wang, Haixia Wang:
Pull-off buffer: Borrowing cache space to avoid deadlock for fault-tolerant NoC routing. 464-471 - Xia Zhao, Sheng Ma, Chen Li, Lieven Eeckhout, Zhiying Wang:
A heterogeneous low-cost and low-latency Ring-Chain network for GPGPUs. 472-479 - Vasil Pano, Isikcan Yilmaz, Ankit More, Baris Taskin:
Energy aware routing of multi-level Network-on-Chip traffic. 480-486 - Khondker Zakir Ahmed, Saibal Mukhopadhyay:
A single-inductor-cascaded-stage topology for high conversion ratio boost regulator. 487-491 - Na Gong, Jonathon Edstrom, Dongliang Chen, Jinhui Wang:
Data-Pattern enabled Self-Recovery multimedia storage system for near-threshold computing. 492-498 - Samira Ataei, James E. Stine
A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS. 499-506 - Bruce M. Fleischer, Christos Vezyrtzis, Karthik Balakrishnan, Keith A. Jenkins:
A statistical critical path monitor in 14nm CMOS. 507-511 - Xian Zhu, Mihir Awatramani, Diane T. Rover, Joseph Zambreno:
ONAC: Optimal number of active cores detector for energy efficient GPU computing. 512-519 - Peng Gu, Dylan C. Stow, Russell Barnes, Eren Kursun, Yuan Xie:
Thermal-aware 3D design for side-channel information leakage. 520-527 - Sudarshan Srinivasan, Israel Koren, Sandip Kundu
Improving performance per Watt of non-monotonic Multicore Processors via bottleneck-based online program phase classification. 528-535 - David J. Schlais, Mikko H. Lipasti:
BADGR: A practical GHR implementation for TAGE branch predictors. 536-543 - George Papadimitriou, Dimitris Gizopoulos, Athanasios Chatzidimitriou, Tom Kolan, Anatoly Koyfman, Ronny Morad, Vitali Sokhin:
Unveiling difficult bugs in address translation caching arrays for effective post-silicon validation. 544-551 - Gabriel A. G. Andrade, Marleson Graf, Luiz C. V. dos Santos
Chain-based pseudorandom tests for pre-silicon verification of CMP memory systems. 552-559 - Yongjian Li, Kaiqiang Duan, Yi Lv, Jun Pang, Shaowei Cai:
A novel approach to parameterized verification of cache coherence protocols. 560-567 - Changgong Li, Alexander Schwarz, Christian Hochberger:
A readback based general debugging framework for soft-core processors. 568-575 - Yan Sui, Chun Yang, Dong Tong, Xianhua Liu
MFAP: Fair Allocation between fully backlogged and non-fully backlogged applications. 576-583 - Omid Assare, Rajesh K. Gupta:
Strategies for optimal operating point selection in timing speculative processors. 584-591 - Akramul Azim, Sebastian Fischmeister:
Efficient mode changes in multi-mode systems. 592-599 - Vinayaka Jyothi, Manasa Thoonoli, Richard Stern, Ramesh Karri
FPGA Trust Zone: Incorporating trust and reliability into FPGA designs. 600-605 - Daniel Große
Guided lightweight Software test qualification for IP integration using Virtual Prototypes. 606-613 - Martí Anglada, Ramon Canal
MASkIt: Soft error rate estimation for combinational circuits. 614-621 - Jack Wadden, Nathan Brunelle, Ke Wang, Mohamed El-Hadedy, Gabriel Robins, Mircea Stan
Generating efficient and high-quality pseudo-random behavior on Automata Processors. 622-629 - Saumya Chandra, Ramkumar Jayaseelan, Ravi Bhargava:
Speculative path power estimation using trace-driven simulations during high-level design phase. 630-637 - Ayaz Akram, Lina Sawalha:
×86 computer architecture simulators: A comparative study. 638-645 - Chen Li, Sheng Ma, Lu Wang, Zicong Wang, Xia Zhao, Yang Guo:
DLL: A dynamic latency-aware load-balancing strategy in 2.5D NoC architecture. 646-653 - S. Karen Khatamifard, Michael Resch, Nam Sung Kim, Ulya R. Karpuzcu:
VARIUS-TC: A modular architecture-level model of parametric variation for thin-channel switches. 654-661 - Tianjian Li, Li Jiang, Naifeng Jing, Nam Sung Kim, Xiaoyao Liang:
CNFET-based high throughput register file architecture. 662-669 - Emre Neftci:
Stochastic neuromorphic learning machines for weakly labeled data. 670-673 - Chang Song, Beiye Liu, Chenchen Liu, Hai Li
Design techniques of eNVM-enabled neuromorphic computing systems. 674-677 - Zhe Li, Ao Ren, Ji Li, Qinru Qiu, Yanzhi Wang, Bo Yuan:
DSCNN: Hardware-oriented optimization for Stochastic Computing based Deep Convolutional Neural Networks. 678-681 - Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Ram Krishnamurthy:
Ultra-low energy security circuits for IoT applications. 682-685 - Monodeep Kar, Arvind Singh, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
What does ultra low power requirements mean for side-channel secure cryptography? 686-689 - Sandip Ray, Tamzidul Hoque, Abhishek Basak, Swarup Bhunia
The power play: Security-energy trade-offs in the IoT regime. 690-693
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