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ISLPED 2003: Seoul, Korea
- Ingrid Verbauwhede, Hyung Roh:
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003. ACM 2003, ISBN 1-58113-682-X
Plenary speeches
- Ki Won Lee:
Low power requirements for future digital life style. 1 - Tsugio Makimoto, Yoshio Sakai:
Evolution of low power electronics and its future applications. 2-5
Low power caches
- Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy:
A forward body-biased low-leakage SRAM cache: device and architecture considerations. 6-9 - Lawrence T. Clark, Byungwoo Choi, Michael W. Wilkerson:
Reducing translation lookaside buffer active power. 10-13 - Yen-Jen Chang, Chia-Lin Yang, Feipei Lai:
A power-aware SWDR cell for reducing cache write power. 14-17 - Amit Agarwal, Kaushik Roy:
A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. 18-21 - Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel:
Understanding and minimizing ground bounce during mode transition of power gating structures. 22-25
Power modeling and optimization for embedded systems
- Luca Benini, Angelo Galati, Alberto Macii, Enrico Macii, Massimo Poncino:
Energy-efficient data scrambling on memory-processor interfaces. 26-29 - Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Analyzing the energy consumption of security protocols. 30-35 - Inseok Choi, Hyung Soo Kim, Heonshik Shin, Naehyuck Chang:
LPBP: low-power basis profile of the Java 2 Micro Edition. 36-39 - Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Erik Brockmeyer, Francky Catthoor, Mary Jane Irwin:
Estimating influence of data layout optimizations on SDRAM energy consumption. 40-43 - Ravishankar Rao, Sarma B. K. Vrudhula, Daler N. Rakhmatov:
Analysis of discharge techniques for multiple battery systems. 44-47
Design strategies for active power reduction
- Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou:
A 225 MHz resonant clocked ASIC chip. 48-53 - Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy:
Energy recovery clocking scheme and flip-flops for ultra low-energy applications. 54-59 - Juan Antonio Carballo, Jeffrey L. Burns, Seung-Moon Yoo, Ivan Vo, V. Robert Norman:
A semi-custom voltage-island technique and its application to high-speed serial links. 60-65 - Kyu-won Choi, Abhijit Chatterjee:
UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI. 72-77
Leakage estimation
- Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif:
Full chip leakage estimation considering power supply and temperature variations. 78-83 - Rajeev R. Rao, Ashish Srivastava, David T. Blaauw, Dennis Sylvester:
Statistical estimation of leakage current considering inter- and intra-die process variation. 84-89 - Xuning Chen, Li-Shiuan Peh:
Leakage power modeling and optimization in interconnection networks. 90-95 - Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns:
Leakage and leakage sensitivity computation for combinational circuits. 96-99 - Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown:
Efficient techniques for gate leakage estimation. 100-103
Design strategies for controlling standby leakage
- Benton H. Calhoun, Frank Honoré, Anantha P. Chandrakasan:
Design methodology for fine-grained leakage control in MTCMOS. 104-109 - Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae Park, Kyu-Myung Choi, Jeong-Taek Kong:
An MTCMOS design methodology and its application to mobile computing. 110-115 - Cassondra Neau, Kaushik Roy:
Optimal body bias selection for leakage improvement and process compensation over different technology generations. 116-121 - Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar:
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. 122-127 - Nikhil Jayakumar, Sunil P. Khatri:
An ASIC design methodology with predictably low leakage, using leakage-immune standard cells. 128-133
Advances in low power synthesis
- Deming Chen, Jason Cong, Yiping Fan:
Low-power high-level synthesis for FPGA architectures. 134-139 - Feng Gao, John P. Hayes:
ILP-based optimization of sequential circuits for low power. 140-145 - Ankur Srivastava:
Simultaneous Vt selection and assignment for leakage optimization. 146-151 - Azadeh Davoodi, Ankur Srivastava
:
Effective graph theoretic techniques for the generalized low power binding problem. 152-157 - David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. 158-163
Power estimation and design for scaled technologies
- Fujio Ishihara, Farhana Sheikh
Level conversion for dual-supply systems. 164-167 - Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown:
New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. 168-171 - Saibal Mukhopadhyay, Kaushik Roy:
Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation. 172-175 - Kwang-Il Oh, Lee-Sup Kim:
A clock delayed sleep mode domino logic for wide dynamic OR gate. 176-179 - Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang:
Strained-si devices and circuits for low-power applications. 180-183
Low power analog building blocks
- Qadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri:
Low power startup circuits for voltage and current reference with zero steady state current. 184-188 - Woo Young Choi, Jong Duk Lee, Byung-Gook Park:
Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers. 189-192 - Masayuki Miyazaki, Hidetoshi Tanaka, Goichi Ono, Tomohiro Nagano, Norio Ohkubo, Takayuki Kawahara, Kazuo Yano:
Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experiment. 193-198 - Stephen Tang, Siva G. Narendra, Vivek De:
Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation. 199-204
Keynote speech 1
- Sung-Mo Kang:
Elements of low power design for integrated systems. 205-210
Temperature and power aware architectures
- Weiping Liao, Fei Li, Lei He:
Microarchitecture level power and thermal simulation considering temperature dependent leakage model. 211-216 - Seongmoo Heo, Kenneth C. Barr
Reducing power density through activity migration. 217-222 - Michael D. Powell, T. N. Vijaykumar:
Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise. 223-228 - Yiran Chen, Kaushik Roy, Cheng-Kok Koh:
Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. 229-234 - Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin
Reducing reorder buffer complexity through selective operand caching. 235-240 - Tao Li, Lizy Kurian John:
Routine based OS-aware microprocessor resource adaptation for run-time operating system power saving. 241-246
Keynote speech 2
- Werner Weber:
Ambient intelligence: industrial research on a visionary concept. 247-251
Power efficient cache design
- Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau:
Reducing data cache energy consumption via cached load/store queue. 252-257 - Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin, Lizy Kurian John:
On load latency in low-power caches. 258-261 - Gokhan Memik, Glenn Reinman, William H. Mangione-Smith:
Reducing energy and delay using efficient victim caches. 262-265 - Youtao Zhang, Jun Yang:
Low cost instruction cache designs for tag comparison elimination. 266-269 - Jun Yang, Youtao Zhang:
Lightweight set buffer: low power data cache for multimedia application. 270-273 - Carlos Molina, Carles Aliagas, Montse Garcia
Non redundant data cache. 274-277
System estimation and voltage scheduling
- Emil Talpes, Diana Marculescu
A critical analysis of application-adaptive multiple clock processors. 278-281 - Karthik Natarajan, Heather Hanson, Stephen W. Keckler, Charles R. Moore, Doug Burger:
Microprocessor pipeline energy analysis. 282-287 - Pai H. Chou, Chulsung Park, Jae Park, Kien Pham, Jinfeng Liu:
B#: a battery emulator and power profiling instrument. 288-293 - Kavel M. Büyüksahin, Priyadarsan Patra
ESTIMA: an architectural-level power estimator for multi-ported pipelined register files. 294-297 - Amitabh Menon, S. K. Nandy, Mahesh Mehendale:
Multivoltage scheduling with voltage-partitioned variable storage. 298-301 - Azadeh Davoodi, Ankur Srivastava:
Voltage scheduling under unpredictabilities: a risk management paradigm. 302-305
Energy efficient microarchitectural techniques
- Hsien-Hsin S. Lee, Chinnakrishnan S. Ballapuram:
Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning. 306-311 - Jung-Hoon Lee, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim:
A selective filter-bank TLB system. 312-317 - Andreas Moshovos:
Checkpointing alternatives for high performance, power-aware processors. 318-321 - Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno:
Reducing instruction fetch energy with backwards branch control information and buffering. 322-325 - Hajime Shimada, Hideki Ando, Toshio Shimada:
Pipeline stage unification: a low-energy consumption technique for future mobile processors. 326-329 - Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
Energy-efficient instruction set synthesis for application-specific processors. 330-333
High speed converters, amplifiers, and low power analog circuits
- Reza Lotfi, Mohammad Taherzadeh-Sani, M. Yaser Azizi, Omid Shoaei:
A low-power design methodology for high-resolution pipelined analog-to-digital converters. 334-339 - Hesam Amir Aslanzadeh, Saeid Mehrmanesh, Mohammad B. Vahidfar, Amin Quasem Safarian, Reza Lotfi:
A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using "Slew Boost" technique. 340-344 - Mohammad Yavari
Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications. 345-348 - Quoc-Hoang Duong, Trung-Kien Nguyen, Sang-Gug Lee:
Low-voltage low-power high dB-linear CMOS exponential function generator using highly-linear V-I converter. 349-352 - Mohammad M. Ahmadi, Reza Lotfi:
A new architecture for rail-to-rail input constant-gm CMOS operational transconductance amplifiers. 353-358
Keynote speech 3
- James R. Heath:
A systems approach to molecular electronics. 359
Circuit considerations for low power
- Alice Wang, Anantha P. Chandrakasan:
Energy-aware architectures for a real-valued FFT implementation. 360-365 - Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer:
A low-power VLSI architecture for turbo decoding. 366-371 - Venkata Syam P. Rapaka, Diana Marculescu
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores. 372-377 - Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin
Power efficient comparators for long arguments in superscalar processors. 378-383 - Nam Sung Kim, Trevor N. Mudge:
The microarchitecture of a low power register file. 384-389 - Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang
Branch prediction on demand: an energy-efficient solution. 390-395
System level issues
- Woonseok Kim, Jihong Kim, Sang Lyul Min:
Dynamic voltage scaling algorithm for fixed-priority real-time systems using work-demand analysis. 396-401 - Jie S. Hu, A. Nadgir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir:
Exploiting program hotspots and code sequentiality for instruction cache leakage management. 402-407 - Dongkun Shin, Jihong Kim:
Power-aware scheduling of conditional task graphs in real-time multiprocessor systems. 408-413 - Madhavi Gopal Valluri, Lizy Kurian John, Heather Hanson:
Exploiting compiler-generated schedules for energy savings in high-performance processors. 414-419 - Hyung Gyu Lee, Naehyuck Chang:
Energy-aware memory allocation in heterogeneous non-volatile memory systems. 420-423 - Jason Sungtae Kim, Michael Bedford Taylor, Jason E. Miller, David Wentzlaff:
Energy characterization of a tiled architecture processor with on-chip networks. 424-427
Keynote speech 4
- Domine Leenaerts:
Low power RF IC design for wireless communication. 428-433
RF communication circuits
- Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Robert Trzcinski, Mohamed Talbi, John Safran, Asit Ray, Lawrence F. Wagner:
A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate. 434-439 - Jean-Olivier Plouchart, Jonghae Kim, Hector Recoules, Noah Zamdmer, Yue Tan, Melanie Sherony, Asit Ray, Lawrence F. Wagner:
A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technology. 440-442 - Chih-Jen Yen, Mely Chen Chi, Wen-Yaw Chung, Shing-Hao Lee:
A 0.75-mW analog processor IC for wireless biosignal monitor. 443-448 - Drew Guckenberger, Kevin T. Kornegay
Integrated DC-DC converter design for improved WCDMA power amplifier efficiency in SiGe BiCMOS technology. 449-454 - Payam Heydari, Ying Zhang:
A novel high frequency, high-efficiency, differential class-E power amplifier in 0.18mum CMOS. 455-458
Sensor networks and communication systems
- Eun Jung Kim, Ki Hwan Yum, Greg M. Link, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mazin S. Yousif, Chita R. Das:
Energy optimization techniques in cluster interconnects. 459-464 - Flavius Gruian, Krzysztof Kuchcinski:
Uncertainty-based scheduling: energy-efficient ordering for tasks with variable execution time. 465-468 - Sung I. Park, Vijay Raghunathan, Mani B. Srivastava:
Energy efficiency and fairness tradeoffs in multi-resource, multi-tasking embedded systems. 469-474 - Farinaz Koushanfar
Low power coordination in wireless ad-hoc networks. 475-480 - Aman Kansal, Mani B. Srivastava:
An environmental energy harvesting framework for sensor networks. 481-486
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