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ISVLSI 2016: Pittsburgh, PA, USA
- IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016. IEEE Computer Society 2016, ISBN 978-1-4673-9039-2
Analog and Mixed Signal I
- Davit Mirzoyan, Ararat Khachatryan:
A New Process Variation Monitoring Circuit. 1-5 - Vishnu Unnikrishnan
, Mark Vesterbacka:
Mixed-Signal Design Using Digital CAD. 6-11 - Divya Duvvuri, Vijaya Sankara Rao Pasupureddi:
An Integrated Common Gate CTLE Receiver Front End with Charge Mode Adaptation. 12-17
Special Session: FPGA Based Computing: Evolving Applications and Design Tools
- Anupam Chattopadhyay, Vikramkumar Pudi, Anubhab Baksi, Thambipillai Srikanthan:
FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation. 18-23 - Kaiyuan Guo, Lingzhi Sui, Jiantao Qiu, Song Yao, Song Han, Yu Wang, Huazhong Yang:
Angel-Eye: A Complete Design Flow for Mapping CNN onto Customized Hardware. 24-29 - Shaon Yousuf, Ann Gordon-Ross:
An Automated Hardware/Software Co-Design Flow for Partially Reconfigurable FPGAs. 30-35
Computer Aided Design and Verification I
- Renan Netto, Vinicius S. Livramento, Chrystian Guth, Luiz C. V. dos Santos
Speeding up Incremental Legalization with Fast Queries to Multidimensional Trees. 36-41 - Jeongwoo Heo, Taewhan Kim:
Timing Analysis and Optimization Based on Flexible Flip-Flop Timing Model. 42-46 - Heechun Park, Taewhan Kim:
Synthesizing Asynchronous Circuits toward Practical Use. 47-52
Special Session: Cyber-Physical Systems: Architecture and Security in Smart Buildings and Autonomous Driving
- Bowen Zheng, Hengyi Liang, Qi Zhu
Next Generation Automotive Architecture Modeling and Exploration for Autonomous Driving. 53-58 - Hengyang Zhao, Sheldon X.-D. Tan, Hai Wang, Hai-Bao Chen:
Online Unusual Behavior Detection for Temperature Sensor Networks. 59-62 - Kelvin Ly, Yier Jin
Security Challenges in CPS and IoT: From End-Node to the System. 63-68
Digital Circuit Design and FPGA Based Designs I
- Mahesh S. Murty, Rahul Shrestha:
VLSI Architecture for Cyclostationary Feature Detection Based Spectrum Sensing for Cognitive-Radio Wireless Networks and Its ASIC Implementation. 69-74 - Anirban Sengupta, Deepak Kachave:
Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis. 75-80 - Yaojie Lu, Seyed Amin Rooholamin, Sotirios G. Ziavras:
Power-Performance Optimization of a Virtualized SMT Vector Processor via Thread Fusion and Lane Configuration. 81-86
Special Session: From Neural Science to Neuromorphic Computing
- Mark E. Dean, Christopher Daffron:
A VLSI Design for Neuromorphic Computing. 87-92 - Ming Tu, Visar Berisha
Reducing the Model Order of Deep Neural Networks Using Information Theory. 93-98
Emerging and Post-CMOS Technologies I
- Giovanni Causapruno, Umberto Garlando, Fabrizio Cairo, Maurizio Zamboni, Mariagrazia Graziano:
A Reconfigurable Array Architecture for NML. 99-104 - S. Ahish, Dheeraj Sharma, M. H. Vasantha, Kumar Y. B. Nithin
Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor. 105-109 - Chenchen Liu, Qing Yang, Bonan Yan, Jianlei Yang, Xiaocong Du, Weijie Zhu, Hao Jiang, Qing Wu, Mark Barnell, Hai Li
A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy. 110-115
Special Session: Emerging Stochastic Computing: From Arithmetic to Applications
- Te-Hsuan Chen, John P. Hayes:
Design of Division Circuits for Stochastic Computing. 116-121 - Honglan Jiang, Chengkun Shen, Pieter P. Jonker, Fabrizio Lombardi, Jie Han:
Adaptive Filter Design Using Stochastic Circuits. 122-127 - Bo Yuan, Yanzhi Wang:
High-Accuracy FIR Filter Design Using Stochastic Computing. 128-133
System Design and Security I
- Cédric Marchand
Design and Characterization of the TERO-PUF on SRAM FPGAs. 134-139 - Festus Hategekimana, Pierre-Alexis Nardin, Christophe Bobda:
Hardware/Software Isolation and Protection Architecture for Transparent Security Enforcement in Networked Devices. 140-145 - B. Naresh Kumar Reddy
A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core. 146-151
Testing, Reliability, and Fault-Tolerance I
- Cunxi Yu, Maciej J. Ciesielski:
Analyzing Imprecise Adders Using BDDs - A Case Study. 152-157 - Tiantao Lu, Zhiyuan Yang, Ankur Srivastava
Post-Placement Optimization for Thermal-Induced Mechanical Stress Reduction. 158-163 - Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell:
Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI - LVT and RVT Configurations. 164-169
Digital Circuit Design and FPGA Based Designs II
- Sayed El Gendy, Ahmed Shalaby
Low Cost VLSI Architecture for Sample Adaptive Offset Encoder in HEVC. 170-175 - Yaohua Wang, Xiaowen Chen, Dong Wang, Sheng Liu:
Dynamic Per-Warp Reconvergence Stack for Efficient Control Flow Handling in GPUs. 176-181 - Weiwei Shi, Zhao Guangdong, Oliver Chiu-sing Choy:
Subthreshold Passive RFID Tag's Baseband Processor Core Design with Custom Modules and Cells. 182-187
Special Session: Emerging Devices for Hardware Security: Fiction or Future
- Hao-Ting Shen, Fahim Rahman, Bicky Shakya, Mark M. Tehranipoor, Domenic Forte
Selective Enhancement of Randomness at the Materials Level: Poly-Si Based Physical Unclonable Functions (PUFs). 188-193 - Garrett S. Rose
A Designer's Rationale for Nanoelectronic Hardware Security Primitives. 194-199 - Kaveh Shamsi, Wujie Wen, Yier Jin
Hardware Security Challenges Beyond CMOS: Attacks and Remedies. 200-205
System Design and Security II
- Alec Roelke, Mircea R. Stan
Attacking an SRAM-Based PUF through Wearout. 206-211 - Mesbah Uddin, Md. Badruddoja Majumder, Garrett S. Rose
Techniques for Improved Reliability in Memristive Crossbar PUF Circuits. 212-217 - Siva Nishok Dhanuskodi, Shahrzad Keshavarz, Daniel E. Holcomb:
LLPA: Logic State Based Leakage Power Analysis. 218-223
Special Session: The Smart-Everything Era
- Andrea Solazzo, Emanuele Del Sozzo
Hardware Design Automation of Convolutional Neural Networks. 224-229 - Grégoire Surrel, Francisco J. Rincón, Srinivasan Murali, David Atienza:
Low-Power Wearable System for Real-Time Screening of Obstructive Sleep Apnea. 230-235 - Renzo Andri, Lukas Cavigelli
YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights. 236-241
System Design and Security III
- Kapil Dev, Sherief Reda, Indrani Paul
Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs. 242-247 - Yousra Alkabani, Zach Koopmans, Haifeng Xu, Alex K. Jones
Write Pulse Scaling for Energy Efficient STT-MRAM. 248-253 - Papa-Sidi Ba, Sophie Dupuis, Palanichamy Manikandan
Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique. 254-259
Emerging and Post-CMOS Technologies II
- Pratima Chatterjee, Mayukh Sarkar
Computing in Ribosomes: Performing Boolean Logic Using mRNA-Ribosome System. 260-265 - Bohua Li, Yukui Pei, Wujie Wen:
Efficient Low-Density Parity-Check (LDPC) Code Decoding for Combating Asymmetric Errors in STT-RAM. 266-271 - Khadeer Ahmed, Amar Shrestha, Yanzhi Wang, Qinru Qiu:
System Design for In-Hardware STDP Learning and Spiking Based Probablistic Inference. 272-277
Computer Aided Design and Verification II
- Niels Thole, Görschwin Fey
A Hybrid Algorithm to Conservatively Check the Robustness of Circuits. 278-283 - Cunxi Yu, Maciej J. Ciesielski:
Formal Verification Using Don't-Care and Vanishing Polynomials. 284-289 - Jucemar Monteiro, Nima Karimpour Darav, Guilherme Flach, Mateus Fogaça
Routing-Aware Incremental Timing-Driven Placement. 290-295
Special Session: Explorations in Energy Efficient Computing from Circuits to Systems
- Peipei Yin, Chenghua Wang, Weiqiang Liu, Fabrizio Lombardi:
Design and Performance Evaluation of Approximate Floating-Point Multipliers. 296-301 - Umar Albalawi, Saraju P. Mohanty, Elias Kougianos:
Energy-Efficient Design of the Secure Better Portable Graphics Compression Architecture for Trusted Image Communication in the IoT. 302-307 - S. Dinesh Kumar, Himanshu Thapliyal
Energy-Efficient and Secure S-Box Circuit Using Symmetric Pass Gate Adiabatic Logic. 308-313
and Kalyan S. Perumalla Digital Circuit Design and FPGA Based Designs II
- Maher Abdelrasoul, Mohammed Sharaf Sayed, Victor Goulart:
Scalable Integer DCT Architecture for HEVC Encoder. 314-318 - F. Lalchhandama, Brojo Gopal Sapui, Kamalika Datta:
An Improved Approach for the Synthesis of Boolean Functions Using Memristor Based IMPLY and INVERSE-IMPLY Gates. 319-324 - Rengarajan Ragavan, Cédric Killian, Olivier Sentieys:
Adaptive Overclocking and Error Correction Based on Dynamic Speculation Window. 325-330 - Pankaj Verma, Rohit Halba, Hemant Patel, Maryam Shojaei Baghini:
On-Chip Delay Measurement Circuit for Reliability Characterization of SRAM. 331-336
Analog and Mixed Signal II
- Sohail Ahasan, Saurav Maji, Kaushik Roy, Mrigank Sharad:
Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple. 337-342 - S. M. Mayur, Siddharth R. K.
Design of Low Power 5-Bit Hybrid Flash ADC. 343-348 - Sunil Kumar Maddikatla, Srivatsava Jandhyala:
An Accurate All CMOS Temperature Sensor for IoT Applications. 349-354 - Sanjay Singh Rajput, Ashish Singh, Ashwani Kumar Chandel, Rajeevan Chandel
Design of Low-Power High-Gain Operational Amplifier for Bio-Medical Applications. 355-360
Poster Session
- Irith Pomeranz:
A Compact Set of Seeds for LFSR-Based Test Generation from a Fully-Specified Compact Test Set. 361-366 - Raghava Katreepalli
Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design. 367-372 - Xinghua Yang, Yue Xing, Fei Qiao, Qi Wei, Huazhong Yang:
Approximate Adder with Hybrid Prediction and Error Compensation Technique. 373-378 - Rajshekar Kalayappan, Smruti R. Sarangi:
SecCheck: A Trustworthy System with Untrusted Components. 379-384 - Yuanchang Chen, Xinghua Yang, Fei Qiao, Jie Han, Qi Wei, Huazhong Yang:
A Multi-accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis. 385-390 - Marek Parfieniuk
On Area-Efficient Implementation of Data Delays in 7 Series Xilinx FPGAs. 391-396 - Tosiron Adegbija, Ann Gordon-Ross:
Phase-Based Dynamic Instruction Window Optimization for Embedded Systems. 397-402 - Mingyu Li, Jiajun Shi, Mostafizur Rahman, Santosh Khasanvis, Sachin Bhat, Csaba Andras Moritz:
Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit Technology. 403-408 - Kibum Lee, S. Simon Wong:
Fault-Tolerant FPGA with Column-Based Redundancy and Power Gating Using RRAM. 409-414 - Ensar Vahapoglu, Mustafa Altun
Accurate Synthesis of Arithmetic Operations with Stochastic Logic. 415-420 - Mahdi Elghazali, Manoj Sachdev, Ajoy Opal:
A Low-Leakage, Robust ESD Clamp with Thyristor Delay Element in 65 nm CMOS Technology. 421-425 - Sheng Liu, Haiyan Chen, Jianghua Wan, Yaohua Wang:
Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs. 426-430 - Suman Deb, Anupam Chattopadhyay, Hao Yu:
Energy Optimization of Racetrack Memory-Based SIMON Block Cipher. 431-436 - Muhammed Ceylan Morgül
Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays. 437-442 - Maria I. Mera Collantes
Threshold-Dependent Camouflaged Cells to Secure Circuits Against Reverse Engineering Attacks. 443-448 - Jiajun Shi, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Csaba Andras Moritz:
On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICs. 449-454 - Nan Wu
A Real-Time and Energy-Efficient Implementation of Difference-of-Gaussian with Flexible Thin-Film Transistors. 455-460 - Chinmay Deshpande, Bilgiday Yuce, Nahid Farhady Ghalaty, Dinesh Ganta, Patrick Schaumont
A Configurable and Lightweight Timing Monitor for Fault Attack Detection. 461-466 - Andrew Whetzel, Mircea R. Stan
Gate Overdrive with Split-Circuit Biasing to Substitute for Body Biasing in FinFET and UTB FDSOI Circuits. 467-472 - Madhav Rao, Neha Oraon:
Analysis of Switching Energy and Delay for Magnetic Logic Devices. 473-478 - Po-Tsang Chen, Ching-Yuan Yang:
A 90-nm CMOS Frequency Synthesizer with a Tripler for 60-GHz Wireless Communication Systems. 479-483 - Ioannis S. Stamelakos, Amin Khajeh, Ahmed M. Eltawil
A System-Level Exploration of Power Delivery Architectures for Near-Threshold Manycores Considering Performance Constraints. 484-489 - Attila Kinali
Fault-Tolerant Clock Synchronization with High Precision. 490-495 - Avik Bose
STA: A Highly Scalable Low Latency Butterfly Fat Tree Based 3D NoC Design. 496-501 - Juan Sebastian Piedrahita Giraldo, Luigi Carro, Stephan Wong, Antonio C. S. Beck:
Leveraging Compiler Support on VLIW Processors for Efficient Power Gating. 502-507 - A. Purushothaman:
MINLP Based Power Optimization for Pipelined ADC. 508-511 - Yunxi Guo, Akhilesh Tyagi:
Voice Based User-Device Physical Unclonable Functions for Mobile Device Authentication. 512-517 - Manish Kumar Jaiswal, Hayden Kwok-Hay So
Taylor Series Based Architecture for Quadruple Precision Floating Point Division. 518-523 - Sunil Kumar Maddikatla, Srivatsava Jandhyala:
An Accurate All CMOS Bandgap Reference Voltage with Integrated Temperature Sensor for IoT Applications. 524-528 - Kanchan Manna, Chatla Swamy Sagar, Santanu Chattopadhyay, Indranil Sengupta:
Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs. 529-534 - Ningxi Liu, Benton H. Calhoun:
Design Optimization of Register File Throughput and Energy Using a Virtual Prototyping (ViPro) Tool. 535-540 - Xuanle Ren, Ronald D. Blanton, Vítor Grade Tavares
A Learning-Based Approach to Secure JTAG Against Unseen Scan-Based Attacks. 541-546 - Xiaolin Xu, Wayne P. Burleson, Daniel E. Holcomb:
Using Statistical Models to Improve the Reliability of Delay-Based PUFs. 547-552 - Kelson Gent, Michael S. Hsiao:
Fast Multi-level Test Generation at the RTL. 553-558 - Maria Malik, Farnoud Farahmand, Paul Otto, Nima Akhlaghi, Tinoosh Mohsenin, Siddhartha Sikdar
Architecture Exploration for Energy-Efficient Embedded Vision Applications: From General Purpose Processor to Domain Specific Accelerator. 559-564 - Jaya Dofe, Yuejun Zhang, Qiaoyan Yu:
DSD: A Dynamic State-Deflection Method for Gate-Level Netlist Obfuscation. 565-570 - Faris S. Alghareb
Soft Error Effect Tolerant Temporal Self-Voting Checkers: Energy vs. Resilience Tradeoffs. 571-576 - Vinamra Benara, Suresh Purini:
Accurus: A Fast Convergence Technique for Accuracy Configurable Approximate Adder Circuits. 577-582
Student Research Forum
- Kanchan Manna, Santanu Chattopadhyay, Indranil Sengupta:
Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional Networks-on-Chip. 583-586 - Zhou Zhao, Ashok Srivastava, Lu Peng, Saraju P. Mohanty:
A Low-Cost Mixed Clock Generator for High Speed Adiabatic Logic. 587-590 - B. G. Sileshi, Joan Oliver
Accelerating Particle Filter on FPGA. 591-594 - Junghoon Oh, Mineo Kaneko:
Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components. 595-600
System Design and Security IV
- Cezar Reinbrecht, Altamiro Amadeu Susin, Lilian Bossuet, Johanna Sepúlveda:
Gossip NoC - Avoiding Timing Side-Channel Attacks through Traffic Management. 601-606 - Gayathri Ananthanarayanan, Smruti R. Sarangi, M. Balakrishnan:
Leakage Power Aware Task Assignment Algorithms for Multicore Platforms. 607-612 - Prasanna Kansakar, Arslan Munir
A Design Space Exploration Methodology for Parameter Optimization in Multicore Processors. 613-618
Special Session: Technology-aware Mapping of Algorithm to Architecture for Power, Performance, and Reliability
- Zheng Wang, Alessandro Littarru, Emmanuel Ikechukwu Ugwu, Shazia Kanwal, Anupam Chattopadhyay:
Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant Graphs. 619-624 - Tso-Bing Juang, Ying-Ren Lee:
Seamlessly Pipelined Shift-and-Add Circuits Based on Precise Delay Analysis and Its Applications. 625-630 - Anjana Balachandran, Nandeesha Veeranna, Benjamin Carrión Schäfer:
On Time Redundancy of Fault Tolerant C-Based MPSoCs. 631-636
Emerging and Post-CMOS Technologies III
- Dylan C. Stow, Itir Akgun
Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space. 637-642 - Ruizhe Cai, Ao Ren, Yanzhi Wang, Bo Yuan:
Memristor-Based Discrete Fourier Transform for Improving Performance and Energy Efficiency. 643-648 - Sumitha George, Ahmedullah Aziz
Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors. 649-654
Special Session: Scalable Design Approach
- Satyajit Das
A Scalable Design Approach to Efficiently Map Applications on CGRAs. 655-660 - Tan Nguyen, Yao Chen
SoC, NoC and Hierarchical Bus Implementations of Applications on FPGAs Using the FCUDA Flow. 661-666 - Mohammad Tahghighi, Wei Zhang
Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing. 667-672
Computer Aided Design and Verification III
- Chi-Hung Lin, Chia-Shiang Chen, Yu-He Chang, Yu Ting Zhang, Shang-Rong Fang, Santanu Santra, Rung-Bin Lin:
Design Space Exploration of FinFETs with Double Fin Heights for Standard Cell Library. 673-678 - Infall Syafalni
Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM. 679-684 - Amit Ranjan Trivedi, Susmita Dey Manasi:
A Comparative Study of Si/Ge and GaSb/InAs Tunnel FET-Based Cellular Neural Network. 685-690
Digital Circuit Design and FPGA Based Designs III
- Xiaowen Wang, William H. Robinson
A Dual-Threshold Voltage Approach for Timing Speculation in CMOS Circuits. 691-696 - Oana Boncalo, Ioana Mot:
Multi Clock Flooded LDPC Decoding Architecture with Reduced Memory and Interconnect. 697-700 - Rafael Fao de Moura, Jeckson Dellagostin Souza, Luigi Carro, Antonio Carlos Schneider Beck, Mateus Beck Rutzig
The Impact of Heterogeneity on a Reconfigurable Multicore System. 701-706
Digital Circuit Design and FPGA Based Designs IV A Pruning Technique for B&B Based Design Exploration of Approximate Computing
- Mario Barbareschi
A Pruning Technique for B&B Based Design Exploration of Approximate Computing Variants. 707-712 - Mohammed Alawad
Stochastic-Based Convolutional Networks with Reconfigurable Logic Fabric. 713-718 - Monther Abusultan, Sunil P. Khatri:
A Ternary-Valued, Floating Gate Transistor-Based Circuit Design Approach. 719-724
Testing, Reliability, and Fault-Tolerance II
- Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Praveen Raghavan, Francky Catthoor, Wim Dehaene:
Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability. 725-730 - Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel
Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study. 731-736 - Ji Li, Jeffrey T. Draper:
Joint Soft-Error-Rate (SER) Estimation for Combinational Logic and Sequential Elements. 737-742
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