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Pramod Kumar Meher
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- affiliation: C. V. Raman College of Engineering, Bhubaneswar, India
- affiliation: Nanyang Technological University, Singapore
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2020 – today
- 2024
- [j118]Srikant Kumar Beura, Bishnulatpam Pushpa Devi, Prabir Saha
, Pramod Kumar Meher:
Design of a Novel Inexact 4:2 Compressor and Its Placement in the Partial Product Array for Area, Delay, and Power-Efficient Approximate Multipliers. Circuits Syst. Signal Process. 43(6): 3748-3774 (2024) - [j117]Dibakar Pradhan, Pramod Kumar Meher
Input-Output Scheduling and Control for Efficient FPGA Realization of Digit-Serial Multiplication Over Generic Binary Extension Fields. Circuits Syst. Signal Process. 43(12): 7729-7749 (2024) - [j116]Mohammed Yusuf Ansari
Advancements in Deep Learning for B-Mode Ultrasound Segmentation: A Comprehensive Review. IEEE Trans. Emerg. Top. Comput. Intell. 8(3): 2126-2149 (2024) - [j115]Shouharda Ghosh
Low Complexity Design of Logistic Distance Metric Adaptive Filter for Impulsive Noise Environments. IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1409-1413 (2024) - [c68]Anil Kali, Samrat L. Sabat, Pramod Kumar Meher:
A Novel DA-Based Parallel Architecture for Inner-Product of Variable Vectors. ISCAS 2024: 1-5 - [c67]Jayashree Rana, Pramod Kumar Meher, Rojalina Priyadarshini, K. Pratyush Rao:
Efficient Implementation of Entity On-Boarding and Authentication in Zero-Trust Systems. PKIA 2024: 1-6 - 2023
- [j114]Mohammed Yusuf Ansari
Dense-PSP-UNet: A neural network for fast inference liver ultrasound segmentation. Comput. Biol. Medicine 153: 106478 (2023) - [j113]Anu Verma
An Efficient Scaling-Free Folded Hyperbolic CORDIC Design Using a Novel Low-Complexity Power-of-2 Taylor Series Approximation. IEEE Trans. Very Large Scale Integr. Syst. 31(8): 1167-1177 (2023) - [j112]Anil Kali
Low-Complexity Distributed Arithmetic-Based Architecture for Inner-Product of Variable Vectors. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1368-1376 (2023) - 2022
- [j111]Sun Sik Lee, Thanh Dat Nguyen, Pramod Kumar Meher
Energy-Efficient High-Speed ASIC Implementation of Convolutional Neural Network Using Novel Reduced Critical-Path Design. IEEE Access 10: 34032-34045 (2022) - [j110]Supriya Aggarwal
Enhanced Sharpening of CIC Decimation Filters, Implementation and Applications. Circuits Syst. Signal Process. 41(8): 4581-4603 (2022) - 2021
- [j109]Su Min Cho
Design of Very High-Speed Pipeline FIR Filter Through Precise Critical Path Analysis. IEEE Access 9: 34722-34735 (2021) - 2020
- [j108]Maher Jridi
Efficient approximate core transform and its reconfigurable architectures for HEVC. J. Real Time Image Process. 17(2): 329-339 (2020) - [j107]Dwaipayan Ray
An Analytical Framework and Approximation Strategy for Efficient Implementation of Distributed Arithmetic-Based Inner-Product Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 212-224 (2020) - [j106]Basant Kumar Mohanty
An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1221-1229 (2020) - [j105]Dwaipayan Ray
Analysis and Design of Unified Architectures for Zero-Attraction-Based Sparse Adaptive Filters. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1321-1325 (2020)
2010 – 2019
- 2019
- [j104]Subhendu Kumar Sahoo, Pramod Kumar Meher, Ganesh Kumar Ganjikunta
Multichannel Filters for Wireless Networks: Lookup-Table-Based Efficient Implementation. IEEE Consumer Electron. Mag. 8(3): 44-49 (2019) - [j103]Bimal Kumar Meher, Pramod Kumar Meher:
Analysis of Systolic Penalties and Design of Efficient Digit-Level Systolic-like Multiplier for Binary Extension Fields. Circuits Syst. Signal Process. 38(2): 774-790 (2019) - [j102]G. Ganesh Kumar
50 Years of FFT Algorithms and Applications. Circuits Syst. Signal Process. 38(12): 5665-5698 (2019) - [j101]Basant K. Mohanty
Area-Delay-Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 1042-1050 (2019) - [j100]Jiafeng Xie
Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2119-2130 (2019) - [c66]Dwaipayan Ray
Analysis and Design of Approximate Inner-Product Architectures Based on Distributed Arithmetic. ISCAS 2019: 1-5 - [c65]Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher:
Low-Complexity Systolic Multiplier for GF(2m) using Toeplitz Matrix-Vector Product Method. ISCAS 2019: 1-5 - [c64]Sumit Satyavijay Wadkar, Bishnu Prasad Das, Pramod Kumar Meher:
Low Latency Scaling-Free Pipeline CORDIC Architecture Using Augmented Taylor Series. iSES 2019: 312-315 - 2018
- [j99]Syed Naveen Altaf Ahmed, Pramod Kumar Meher, Achutavarrier Prasad Vinod
Efficient Cross-Correlation Algorithm and Architecture for Robust Synchronization in Frame-Based Communication Systems. Circuits Syst. Signal Process. 37(6): 2548-2573 (2018) - [j98]Dwaipayan Ray
Efficient Shift-Add Implementation of FIR Filters Using Variable Partition Hybrid Form Structures. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4247-4257 (2018) - [j97]Bhavan A. Jasani, Siew-Kei Lam
Threshold-Guided Design and Optimization for Harris Corner Detector Architecture. IEEE Trans. Circuits Syst. Video Technol. 28(12): 3516-3526 (2018) - [j96]Jiafeng Xie
Low Register-Complexity Systolic Digit-Serial Multiplier Over GF(2m) Based on Trinomials. IEEE Trans. Multi Scale Comput. Syst. 4(4): 773-783 (2018) - 2017
- [j95]Xin Lou
Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(2): 313-324 (2017) - [j94]Pramod Kumar Meher, Xin Lou:
Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2): 399-408 (2017) - [j93]Jiafeng Xie
Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over GF(2m) Based on NIST Polynomials. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(7): 1815-1825 (2017) - [j92]Xin Lou
Novel Structure for Area-Efficient Implementation of FIR Filters. IEEE Trans. Circuits Syst. II Express Briefs 64-II(10): 1212-1216 (2017) - [j91]Maher Jridi
Scalable Approximate DCT Architectures for Efficient HEVC-Compliant Video Coding. IEEE Trans. Circuits Syst. Video Technol. 27(8): 1815-1825 (2017) - [j90]Chiou-Yng Lee
Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 735-746 (2017) - [c63]Subhendu Kumar Sahoo, Pramod Kumar Meher:
Lookup Table-Based Low-Power Implementation of Multi-channel Filters for Software Defined Radio. iNIS 2017: 23-27 - 2016
- [j89]Pramod Kumar Meher:
Seamless Pipelining of DSP Circuits. Circuits Syst. Signal Process. 35(4): 1147-1162 (2016) - [j88]Basant Kumar Mohanty
A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic. Integr. 54: 37-46 (2016) - [j87]Chiou-Yng Lee
Comment on "Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2m) Using Generalized (a, b)-Way Karatsuba Algorithm". IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8): 1316-1319 (2016) - [j86]Xin Lou, Ya Jun Yu, Pramod Kumar Meher:
Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(10): 1701-1713 (2016) - [j85]Nikolaos V. Boulgouris, David R. Bull, Marco Cagnazzo, Andrea Cavallaro, Gene Cheung, Amit K. Roy-Chowdhury, Pedro Comesaña Alfaro, Shan Du, Sarp Ertürk, Markus Flierl, Gian Luca Foresti, Gang Hua, Zhu Li, Weisi Lin, Siwei Ma, Pramod Kumar Meher, Debargha Mukherjee, Aleksandra Pizurica, Andrea Prati, Paolo Remagnino, Arun Ross, Shin'ichi Satoh, Andreas E. Savakis, Heiko Schwarz, Ling Shao, Shervin Shirmohammadi, Giuseppe Valenzise, Meng Wang, Zhou Wang, Yonggang Wen, Dong Xu, Junsong Yuan, Yuan Yuan:
Introduction of New Associate Editors. IEEE Trans. Circuits Syst. Video Technol. 26(2): 253-263 (2016) - [j84]Basant Kumar Mohanty
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 444-452 (2016) - [j83]Pramod Kumar Meher:
On Efficient Retiming of Fixed-Point Circuits. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1257-1265 (2016) - [j82]Supriya Aggarwal
Concept, Design, and Implementation of Reconfigurable CORDIC. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1588-1592 (2016) - [j81]Basant K. Mohanty
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1926-1935 (2016) - [j80]Chiou-Yng Lee, Pramod Kumar Meher, Chung-Hsin Liu:
Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2413-2425 (2016) - 2015
- [j79]Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao:
High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(1): 110-119 (2015) - [j78]Maher Jridi
A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 449-457 (2015) - [j77]Chiou-Yng Lee, Pramod Kumar Meher:
Efficient Subquadratic Space Complexity Architectures for Parallel MPB Single- and Double-Multiplications for All Trinomials Using Toeplitz Matrix-Vector Product Decomposition. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 854-862 (2015) - [j76]Xin Lou, Ya Jun Yu, Pramod Kumar Meher:
Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 863-872 (2015) - [j75]Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao:
Low-Latency High-Throughput Systolic Multipliers Over GF(2m) for NIST Recommended Pentanomials. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 881-890 (2015) - [j74]Chiou-Yng Lee, Pramod Kumar Meher:
Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2m) Using Generalized (a, b)-Way Karatsuba Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4): 1091-1098 (2015) - [j73]Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Pramod Kumar Meher:
Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation. IEEE Trans. Circuits Syst. II Express Briefs 62-II(5): 466-470 (2015) - [j72]Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao:
High-Throughput Digit-Level Systolic Multiplier Over GF(2m) Based on Irreducible Trinomials. IEEE Trans. Circuits Syst. II Express Briefs 62-II(5): 481-485 (2015) - [j71]Chung-Hsin Liu, Chiou-Yng Lee, Pramod Kumar Meher:
Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2044-2051 (2015) - [j70]Xin Lou, Ya Jun Yu, Pramod Kumar Meher:
New Approach to the Reduction of Sign-Extension Overhead for Efficient Implementation of Multiple Constant Multiplications. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(11): 2695-2705 (2015) - [j69]Pramod Kumar Meher, Basant Kumar Mohanty
Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(12): 2836-2845 (2015) - [j68]Chiou-Yng Lee, Pramod Kumar Meher:
Area-Efficient Subquadratic Space-Complexity Digit-Serial Multiplier for Type-II Optimal Normal Basis of GF(2m) Using Symmetric TMVP and Block Recombination Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(12): 2846-2855 (2015) - [j67]Hassan Rabah
FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2209-2220 (2015) - [c62]Xin Lou, Pramod Kumar Meher, Ya Jun Yu:
Fine-grained pipelining for multiple constant multiplications. ISCAS 2015: 966-969 - [c61]Basant K. Mohanty
Critical-path optimization for efficient hardware realization of lifting and flipping DWTs. ISCAS 2015: 1186-1189 - [c60]Jeng-Shyang Pan
Efficient subquadratic parallel multiplier based on modified SPB of GF(2m). ISCAS 2015: 1430-1433 - [c59]Pramod Kumar Meher, Basant Kumar Mohanty
Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 Filters. VLSID 2015: 327-332 - 2014
- [j66]Basant K. Mohanty
Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation. IET Image Process. 8(6): 345-353 (2014) - [j65]Basant K. Mohanty
Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(1): 120-133 (2014) - [j64]Yu Pan, Pramod Kumar Meher:
Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(2): 455-462 (2014) - [j63]Pramod Kumar Meher, Sang Yoon Park:
Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(3): 778-788 (2014) - [j62]Sang Yoon Park, Pramod Kumar Meher:
Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter. IEEE Trans. Circuits Syst. II Express Briefs 61-II(7): 511-515 (2014) - [j61]Chiou-Yng Lee, Chun-Sheng Yang, Bimal Kumar Meher, Pramod Kumar Meher, Jeng-Shyang Pan
Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b, 2)-Way Karatsuba Decomposition. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(11): 3115-3124 (2014) - [j60]Chiou-Yng Lee, Pramod Kumar Meher, Chien-Ping Chang:
Efficient $M$ -ary Exponentiation over $GF(2^{m})$ Using Subquadratic KA-Based Three-Operand Montgomery Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(11): 3125-3134 (2014) - [j59]Pramod Kumar Meher, Sang Yoon Park, Basant Kumar Mohanty
Efficient Integer DCT Architectures for HEVC. IEEE Trans. Circuits Syst. Video Technol. 24(1): 168-178 (2014) - [j58]Pramod Kumar Meher, Sang Yoon Park:
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 362-371 (2014) - [c58]Pramod Kumar Meher, Sang Yoon Park:
A novel DA-based architecture for efficient computation of inner-product of variable vectors. ISCAS 2014: 369-372 - [c57]Xin Lou, Ya Jun Yu, Pramod Kumar Meher:
High-speed multiplier block design based on bit-level critical path optimization. ISCAS 2014: 1308-1311 - [c56]Supriya Aggarwal
Reconfigurable CORDIC architectures for multi-mode and multi-trajectory operations. ISCAS 2014: 2490-2494 - [c55]Pramod Kumar Meher, Basant K. Mohanty
Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits. ISCAS 2014: 2628-2631 - [c54]Chiou-Yng Lee, Pramod Kumar Meher, Wen-Yo Lee:
Subquadratic space complexity digit-serial multiplier over binary extension fields using Toom-Cook algorithm. ISIC 2014: 176-179 - 2013
- [j57]Pramod Kumar Meher, Saraju P. Mohanty, A. Prasad Vinod
Guest Editorial: Advanced Techniques for Efficient Electronic System Design. Circuits Syst. Signal Process. 32(6): 2539-2541 (2013) - [j56]Bimal Kumar Meher, Pramod Kumar Meher:
An Efficient Look-up Table-based Approach for Multiplication over GF(2m) Generated by Trinomials. Circuits Syst. Signal Process. 32(6): 2623-2638 (2013) - [j55]Maher Jridi
Zero-quantised discrete cosine transform coefficients prediction technique for intra-frame video encoding. IET Image Process. 7(2): 165-173 (2013) - [j54]Natarajan Sudha, Niladri B. Puhan, Pramod Kumar Meher:
Special section on image and video processing for security. Signal Image Video Process. 7(4): 607-608 (2013) - [j53]Jiafeng Xie, Pramod Kumar Meher, Jianjun He:
Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic. IEEE Trans. Computers 62(6): 1170-1178 (2013) - [j52]Supriya Aggarwal
Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(2): 314-326 (2013) - [j51]Sang Yoon Park, Pramod Kumar Meher:
Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic. IEEE Trans. Circuits Syst. II Express Briefs 60-II(6): 346-350 (2013) - [j50]Jeng-Shyang Pan
Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(12): 3195-3204 (2013) - [j49]Basant K. Mohanty
Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT. IEEE Trans. Circuits Syst. Video Technol. 23(2): 353-363 (2013) - [j48]Basant K. Mohanty
A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm. IEEE Trans. Signal Process. 61(4): 921-932 (2013) - [j47]Jiafeng Xie, Pramod Kumar Meher, Jianjun He:
Low-Complexity Multiplier for GF(2m) Based on All-One Polynomials. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 168-173 (2013) - [j46]Pramod Kumar Meher, Sang Yoon Park:
CORDIC Designs for Fixed Angle of Rotation. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 217-228 (2013) - [j45]Jiafeng Xie, Jianjun He, Pramod Kumar Meher:
Low Latency Systolic Montgomery Multiplier for Finite Field $GF(2^{m})$ Based on Pentanomials. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 385-389 (2013) - [c53]Soni Prattipati, M. N. S. Swamy, Pramod Kumar Meher:
A variable quantization technique for image compression using integer Tchebichef transform. ICICS 2013: 1-5 - [c52]Sang Yoon Park, Pramod Kumar Meher:
Flexible integer DCT architectures for HEVC. ISCAS 2013: 1376-1379 - [c51]Soni Prattipati, Sujata Ishwar, M. N. S. Swamy, Pramod Kumar Meher:
A fast 8×8 integer Tchebichef transform and comparison with integer cosine transform for image compression. MWSCAS 2013: 1294-1297 - 2012
- [j44]Jayakishan Meher
New encoded single-indicator sequences based on physico-chemical parameters for efficient exon identification. Int. J. Bioinform. Res. Appl. 8(1/2): 126-140 (2012) - [j43]Basant K. Mohanty
Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT. IEEE Trans. Circuits Syst. II Express Briefs 59-II(7): 434-438 (2012) - [j42]Francisco Garcia-Herrero, María José Canet, Javier Valls
High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. IEEE Trans. Very Large Scale Integr. Syst. 20(3): 568-573 (2012) - [j41]Supriya Aggarwal
Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1542-1546 (2012) - [j40]Maher Jridi
Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT-Based Image Compression. VLSI Design 2012: 209208:1-209208:12 (2012) - [c50]Syed Naveen Altaf Ahmed, Pramod Kumar Meher, A. Prasad Vinod
A low-complexity spectrum sensing technique for cognitive radios based on correlation of intra-segment decimated vectors. ICCS 2012: 443-447 - [c49]Jiafeng Xie, Pramod Kumar Meher, Jianjun He:
Low-latency area-delay-efficient systolic multiplier over GF(2m) for a wider class of trinomials using parallel register sharing. ISCAS 2012: 89-92 - [c48]Basant K. Mohanty
Efficient architectures for VLSI implementation of 2-D discrete Hadamard transform. ISCAS 2012: 1480-1483 - 2011
- [j39]A. Prasad Vinod
Guest Editorial: Special Issue on Embedded Signal Processing Circuits and Systems for Cognitive Radio-Based Wireless Communication Devices. Circuits Syst. Signal Process. 30(4): 683-688 (2011) - [j38]Francisco Garcia-Herrero, Javier Valls
High-Speed RS(255, 239) Decoder Based on LCC Decoding. Circuits Syst. Signal Process. 30(6): 1643-1669 (2011) - [j37]Jayakishan Meher, Pramod Kumar Meher, Gananath Dash:
Improved Comb Filter based Approach for Effective Prediction of Protein Coding Regions in DNA Sequences. J. Signal Inf. Process. 2(2): 88-99 (2011) - [j36]Jayakishan Meher, Mukesh Kumar Raval, Pramod Kumar Meher, Gananath Dash:
The Role of Combined OSR and SDF Method for Pre-Processing of Microarray Data that Accounts for Effective Denoising and Quantification. J. Signal Inf. Process. 2(3): 190-195 (2011) - [j35]Natarajan Sudha, A. R. Mohan, Pramod Kumar Meher:
A Self-Configurable Systolic Architecture for Face Recognition System Based on Principal Component Neural Network. IEEE Trans. Circuits Syst. Video Technol. 21(8): 1071-1084 (2011) - [j34]Jagdish Chandra Patra
Development of Laguerre Neural-Network-Based Intelligent Sensors for Wireless Sensor Networks. IEEE Trans. Instrum. Meas. 60(3): 725-734 (2011) - [j33]Basant K. Mohanty
Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT. IEEE Trans. Signal Process. 59(5): 2072-2084 (2011) - [j32]Basant K. Mohanty
Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of Frames. IEEE Trans. Signal Process. 59(11): 5605-5616 (2011) - [c47]Chiou-Yng Lee
Speeding up Subquadratic Finite Field Multiplier over GF(2m) Generated by Trinomials Using Toeplitz Matrix-Vector with Inner Product Formula. ICGEC 2011: 232-236 - [c46]Pramod Kumar Meher, Megha Maheshwari:
A high-speed FIR adaptive filter architecture using a modified delayed LMS algorithm. ISCAS 2011: 121-124 - [c45]Yu Pan, Pramod Kumar Meher:
Efficient coefficient partitioning for decomposed DA-based inner-product computation. ISCAS 2011: 406-409 - [c44]Bimal Kumar Meher, Pramod Kumar Meher:
A New Look-Up Table Approach for High-Speed Finite Field Multiplication. ISED 2011: 51-55 - [c43]Pramod Kumar Meher, Yu Pan:
MCM-based implementation of block FIR filters for high-speed and low-power applications. VLSI-SoC 2011: 118-121 - [c42]Pramod Kumar Meher, Sang Yoon Park:
High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic. VLSI-SoC 2011: 428-433 - 2010
- [j31]Chiou-Yng Lee
Efficient bit-parallel multipliers over finite fields GF(2m). Comput. Electr. Eng. 36(5): 955-968 (2010) - [j30]Achutavarrier Prasad Vinod
An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth. Integr. 43(1): 124-135 (2010) - [j29]Pramod Kumar Meher:
New Approach to Look-Up-Table Design and Memory-Based Realization of FIR Digital Filter. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(3): 592-603 (2010) - [j28]Pramod Kumar Meher:
LUT Optimization for Memory-Based Computation. IEEE Trans. Circuits Syst. II Express Briefs 57-II(4): 285-289 (2010) - [j27]Basant K. Mohanty
Parallel and Pipeline Architectures for High-Throughput Computation of Multilevel 3-D DWT. IEEE Trans. Circuits Syst. Video Technol. 20(9): 1200-1209 (2010) - [j26]Chiou-Yng Lee
Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2m) Using Multiple Parity Prediction Schemes. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1234-1238 (2010) - [j25]Pramod Kumar Meher, Jagdish Chandra Patra
Efficient Systolic Designs for 1- and 2-Dimensional DFT of General Transform-Lengths for High-Speed Wireless Communication Applications. J. Signal Process. Syst. 60(1): 1-14 (2010) - [c41]Tso-Bing Juang, Pramod Kumar Meher, Chung-Chun Kuan:
Area-efficient parallel-prefix Ling adders. APCCAS 2010: 736-739 - [c40]Jagdish Chandra Patra
An improved SOM-based visualization technique for DNA microarray data analysis. IJCNN 2010: 1-7 - [c39]Jagdish Chandra Patra
DNA microarray analysis using Equalized Orthogonal Mapping. IJCNN 2010: 1-8 - [c38]Pramod Kumar Meher:
An optimized lookup-table for the evaluation of sigmoid function for artificial neural networks. VLSI-SoC 2010: 91-95 - [c37]Pramod Kumar Meher:
Novel input coding technique for high-precision LUT-based multiplication for DSP applications. VLSI-SoC 2010: 201-206
2000 – 2009
- 2009
- [j24]Jagdish Chandra Patra
Nonlinear channel equalization for wireless communication systems using Legendre neural networks. Signal Process. 89(11): 2251-2262 (2009) - [j23]Pramod Kumar Meher:
Extended Sequential Logic for Synchronous Circuit Optimization and Its Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(4): 469-477 (2009) - [j22]Leena Vachhani
Efficient CORDIC Algorithms and Architectures for Low Area and High Throughput Implementation. IEEE Trans. Circuits Syst. II Express Briefs 56-II(1): 61-65 (2009) - [j21]Pramod Kumar Meher, Javier Valls
50 Years of CORDIC: Algorithms, Architectures, and Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 1893-1907 (2009) - [j20]Leena Vachhani
Efficient FPGA Realization of CORDIC With Application to Robotic Exploration. IEEE Trans. Ind. Electron. 56(12): 4915-4929 (2009) - [j19]Pramod Kumar Meher:
On Efficient Implementation of Accumulation in Finite Field Over GF(2m) and its Applications. IEEE Trans. Very Large Scale Integr. Syst. 17(4): 541-550 (2009) - [j18]Pramod Kumar Meher:
Systolic and Non-Systolic Scalable Modular Designs of Finite Field Multipliers for Reed-Solomon Codec. IEEE Trans. Very Large Scale Integr. Syst. 17(6): 747-757 (2009) - [c36]Pramod Kumar Meher, Yajun Ha, Chiou-Yng Lee
An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials. ASP-DAC 2009: 210-215 - [c35]Jagdish Chandra Patra
Computationally efficient FLANN-based intelligent stock price prediction system. IJCNN 2009: 2431-2438 - [c34]Pramod Kumar Meher:
New Approach to LUT Implementation and Accumulation for Memory-based Multiplication. ISCAS 2009: 453-456 - [c33]Pramod Kumar Meher, Chiou-Yng Lee
Scalable Serial-parallel Multiplier over GF(2m) by Hierarchical Pre-reduction and Input Decomposition. ISCAS 2009: 2910-2913 - 2008
- [j17]Thang Viet Nguyen, Jagdish Chandra Patra
WMicaD: A New Digital Watermarking Technique Using Independent Component Analysis. EURASIP J. Adv. Signal Process. 2008 (2008) - [j16]Pramod Kumar Meher, Basant K. Mohanty
Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform. IEEE Trans. Circuits Syst. II Express Briefs 55-II(2): 151-155 (2008) - [j15]Pramod Kumar Meher:
Systolic and Super-Systolic Multipliers for Finite Field GF(2m) Based on Irreducible Trinomials. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(4): 1031-1040 (2008) - [j14]Jagdish Chandra Patra
Neural-Network-Based Robust Linearization and Compensation Technique for Sensors Under Nonlinear Environmental Influences. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(5): 1316-1327 (2008) - [j13]Pramod Kumar Meher:
New Approach to Scalable Parallel and Pipelined Realization of Repetitive Multiple Accumulations. IEEE Trans. Circuits Syst. II Express Briefs 55-II(9): 902-906 (2008) - [j12]Pramod Kumar Meher:
Parallel and Pipelined Architectures for Cyclic Convolution by Block Circulant Formulation Using Low-Complexity Short-Length Algorithms. IEEE Trans. Circuits Syst. Video Technol. 18(10): 1422-1431 (2008) - [j11]Pramod Kumar Meher, Shrutisagar Chandrasekaran, Abbes Amira:
FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic. IEEE Trans. Signal Process. 56(7-1): 3009-3017 (2008) - [c32]Chiou-Yng Lee
Efficient Bit-Parallel Multipliers in Composite Fields. APSCC 2008: 686-691 - [c31]Pramod Kumar Meher, Jagdish Chandra Patra
Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform. ASAP 2008: 43-48 - [c30]Pramod Kumar Meher:
Efficient systolization of cyclic convolution for systolic implementation of sinusoidal transforms. ASAP 2008: 97-101 - [c29]Basant K. Mohanty
Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transform. ASAP 2008: 162-166 - [c28]Basant K. Mohanty
Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coder. ASAP 2008: 305-309 - [c27]Sujata Ishwar, Pramod Kumar Meher, M. N. S. Swamy:
Discrete tchebichef transform-A fast 4x4 algorithm and its application in image/video compression. ISCAS 2008: 260-263 - [c26]Jagdish Chandra Patra
Content-based image retrieval using orthogonal moments heuristically. SMC 2008: 512-517 - [c25]Jagdish Chandra Patra
Development of intelligent sensors using Legendre functional-link artificial neural networks. SMC 2008: 1140-1145 - [c24]Jagdish Chandra Patra
Determination of QSAR of aldose reductase inhibitors using an RBF network. SMC 2008: 1713-1718 - [c23]Jagdish Chandra Patra
Support vector machine application in drug discovery of aldose reductase inhibitors. SMC 2008: 1731-1736 - [c22]Jagdish Chandra Patra
Legendre-FLANN-based nonlinear channel equalization in wireless communication system. SMC 2008: 1826-1831 - [c21]Jagdish Chandra Patra
Robust CRT-based watermarking technique for authentication of image and document. SMC 2008: 3250-3255 - 2007
- [j10]Pramod Kumar Meher, M. N. S. Swamy:
New Systolic Algorithm and Array Architecture for Prime-Length Discrete Sine Transform. IEEE Trans. Circuits Syst. II Express Briefs 54-II(3): 262-266 (2007) - [j9]Pramod Kumar Meher, Jagdish Chandra Patra
High-Throughput Memory-Based Architecture for DHT Using a New Convolutional Formulation. IEEE Trans. Circuits Syst. II Express Briefs 54-II(7): 606-610 (2007) - [c20]Pramod Kumar Meher:
Systolic Formulation for Low-Complexity Serial-Parallel Implementation of Unified Finite Field Multiplication over GF(2m). ASAP 2007: 134-139 - [c19]Jagdish Chandra Patra
DNA Microarray Data Analysis: Effective Feature Selection for Accurate Cancer Classification. IJCNN 2007: 260-265 - 2006
- [j8]Pramod Kumar Meher:
Highly concurrent reduced-complexity 2-D systolic array for discrete Fourier transform. IEEE Signal Process. Lett. 13(8): 481-484 (2006) - [j7]Pramod Kumar Meher, Thambipillai Srikanthan, Jagdish Chandra Patra
Scalable and modular memory-based systolic architectures for discrete Hartley transform. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(5): 1065-1077 (2006) - [j6]Pramod Kumar Meher:
Efficient Systolic Implementation of DFT Using a Low-Complexity Convolution-Like Formulation. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 702-706 (2006) - [j5]Pramod Kumar Meher:
Hardware-Efficient Systolization of DA-Based Calculation of Finite Digital Convolution. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 707-711 (2006) - [j4]Pramod Kumar Meher:
Unified Systolic-Like Architecture for DCT and DST Using Distributed Arithmetic. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2656-2663 (2006) - [j3]Pramod Kumar Meher:
Systolic Designs for DCT Using a Low-Complexity Concurrent Convolutional Formulation. IEEE Trans. Circuits Syst. Video Technol. 16(9): 1041-1050 (2006) - [c18]Basant K. Mohanty
VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT. APCCAS 2006: 458-461 - [c17]Basant K. Mohanty
Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform. APCCAS 2006: 462-465 - [c16]Pramod Kumar Meher, A. Prasad Vinod
Reduced-Complexity Concurrent Systolic Implementation of the Discrete Sine Transform. APCCAS 2006: 1535-1538 - [c15]A. Prasad Vinod
Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity Analysis. APCCAS 2006: 1547-1550 - [c14]A. Prasad Vinod
Low Power FIR Filter Realization Using Minimal Difference Coefficients: Part II - Algorithm. APCCAS 2006: 1551-1554 - [c13]Pramod Kumar Meher, Jagdish Chandra Patra
A 2-D Systolic Array for High-Throughput Computation of 2-D Discrete Fourier Transform. APCCAS 2006: 1927-1930 - [c12]Jagdish Chandra Patra
An Improved SVD-Based Watermarking Technique for Image and Document Authentication. APCCAS 2006: 1984-1987 - [c11]Jagdish Chandra Patra
Field Programmable Gate Array Implementation of a Neural Network-based Intelligent Sensor System. ICARCV 2006: 1-5 - [c10]Jagdish Chandra Patra, Weineng Lim, Pramod Kumar Meher, Ee-Luang Ang:
Financial Prediction of Major Indices using Computational Efficient Artificial Neural Networks. IJCNN 2006: 2114-2120 - [c9]Jagdish Chandra Patra, Ee-Luang Ang, Pramod Kumar Meher, Qin Zhen:
A New SOM-based Visualization Technique for DNA Microarray Data. IJCNN 2006: 4429-4434 - [c8]Pramod Kumar Meher, Jagdish Chandra Patra:
A new approach to secure distributed storage, sharing and dissemination of digital image. ISCAS 2006 - [c7]Pramod Kumar Meher, Jagdish Chandra Patra, M. R. Meher:
Low-complexity technique for secure storage and sharing of biomedical images. ISCAS 2006 - [c6]Jagdish Chandra Patra, Ee-Luang Ang, Pramod Kumar Meher:
A novel neural network-based linearization and auto-compensation technique for sensors. ISCAS 2006 - 2005
- [j2]Pramod Kumar Meher:
Design of a fully-pipelined systolic array for flexible transposition-free VLSI of 2-D DFT. IEEE Trans. Circuits Syst. II Express Briefs 52-II(2): 85-89 (2005) - [c5]Pramod Kumar Meher:
Area-Time Efficient Systolic Architecture for the DCT. Asia-Pacific Computer Systems Architecture Conference 2005: 787-794 - 2004
- [j1]Nadarajah Sriskanthan, Pramod Kumar Meher, Geok See Ng, C. K. Heng:
WAP-teletext system. IEEE Trans. Consumer Electron. 50(1): 130-138 (2004) - 2003
- [c4]Pramod Kumar Meher, Thambipillai Srikanthan, M. Mahesh Kumar, S. Arunkumar:
Low-Power Transform-Domain Coding by Separable Two-Dimensional Hartley-Like Transform. Embedded Systems and Applications 2003: 228-236 - 2002
- [c3]Prafulla Kumar Behera
Effective communication in ad hoc network of mobile users group. APCCAS (2) 2002: 461-465 - [c2]A. K. Rath, Pramod Kumar Meher:
Reconfigurable execution core for high performance DSP applications. APCCAS (2) 2002: 509-514 - [c1]Prafulla Kumar Behera
Prospects of Group-Based Communication in Mobile Ad hoc Networks. IWDC 2002: 174-183
Coauthor Index
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