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design and verification of asynchronous circuits

Python 51 Updated Apr 26, 2026

A Python tool that compiles neural network weights directly into synthesizable Verilog for the ASIC toolchain.

Python 12 3 Updated Apr 21, 2026

FFmpeg libav tutorial - learn how media works from basic to transmuxing, transcoding and more. Translations: 🇺🇸 🇨🇳 🇰🇷 🇪🇸 🇻🇳 🇧🇷 🇷🇺

C 10,975 1,018 Updated Jan 27, 2026
Jupyter Notebook 7 1 Updated May 6, 2026

A reading list for SRAM-based Compute-In-Memory (CIM) research.

133 8 Updated Oct 29, 2025
C++ 9 1 Updated Aug 26, 2025

Research paper based on or related to ABC.

72 13 Updated Jan 19, 2026

This github repository summarizes relevant papers for shift left techniques in electronic design automation (EDA).

32 1 Updated Sep 19, 2025

Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.

Python 59 9 Updated Aug 23, 2020

An Open-source FPGA IP Generator

Verilog 1,101 199 Updated May 18, 2026

Demo spice library using skywater

CSS 4 10 Updated Sep 27, 2024

HAL – The Hardware Analyzer

C++ 800 92 Updated May 18, 2026

A Python library for designing chips (Photonics, Analog, Quantum, MEMS), PCBs, and 3D-printable objects. We aim to make hardware design accessible, intuitive, and fun—empowering everyone to build t…

Python 933 389 Updated May 16, 2026

LLM-Assisted Hardware Formal Verification Tool

Rust 104 23 Updated May 18, 2026

LEC - Logic Equivalence Checking - Formal Verification

Verilog 40 6 Updated May 17, 2026

ideas and eda software for vlsi design

Python 51 13 Updated May 18, 2026

FPGA Stitching with FABulous and OpenLane 2

Python 4 1 Updated Mar 14, 2024

55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.

Verilog 200 22 Updated Apr 9, 2026

Dyno-IR Monorepo. High-Performance Compiler Framework for HW Synthesis & Beyond.

C++ 11 Updated Apr 27, 2026

Kami - a DSL for designing Hardware in Coq, and the associated semantics and theorems for proving its correctness. Kami is inspired by Bluespec. It is actually a complete rewrite of an older versio…

Coq 8 1 Updated Apr 15, 2025

An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.

C 80 19 Updated Jan 6, 2026

toy technology mapper

C++ 8 1 Updated Feb 13, 2024

Graph data structure library for Rust.

Rust 1 Updated Apr 15, 2026

A minimal development of SSA theory

Lean 237 26 Updated Apr 30, 2026

Codebase for Functional Matching of Logic Subgraphs: Beyond Structural Isomorphism(Neurips25)

Python 6 1 Updated Dec 30, 2025

Algorithms to verify whether a model satisfies a given property.

C++ 5 Updated Aug 30, 2020

FastPoly: An Efficient Polynomial Package for the Verification of Integer Arithmetic Circuits

C++ 14 2 Updated Aug 5, 2025

The Computer History Simulation Project

C 1,858 314 Updated May 18, 2026

A Lean-embedded framework to verify Verilog modules

Lean 13 3 Updated May 8, 2026
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