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design and verification of asynchronous circuits
A Python tool that compiles neural network weights directly into synthesizable Verilog for the ASIC toolchain.
FFmpeg libav tutorial - learn how media works from basic to transmuxing, transcoding and more. Translations: 🇺🇸 🇨🇳 🇰🇷 🇪🇸 🇻🇳 🇧🇷 🇷🇺
A reading list for SRAM-based Compute-In-Memory (CIM) research.
Research paper based on or related to ABC.
This github repository summarizes relevant papers for shift left techniques in electronic design automation (EDA).
Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.
A Python library for designing chips (Photonics, Analog, Quantum, MEMS), PCBs, and 3D-printable objects. We aim to make hardware design accessible, intuitive, and fun—empowering everyone to build t…
LEC - Logic Equivalence Checking - Formal Verification
FPGA Stitching with FABulous and OpenLane 2
55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.
Dyno-IR Monorepo. High-Performance Compiler Framework for HW Synthesis & Beyond.
Kami - a DSL for designing Hardware in Coq, and the associated semantics and theorems for proving its correctness. Kami is inspired by Bluespec. It is actually a complete rewrite of an older versio…
An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
lenianiva / petgraph
Forked from petgraph/petgraphGraph data structure library for Rust.
Codebase for Functional Matching of Logic Subgraphs: Beyond Structural Isomorphism(Neurips25)
Algorithms to verify whether a model satisfies a given property.
FastPoly: An Efficient Polynomial Package for the Verification of Integer Arithmetic Circuits
A Lean-embedded framework to verify Verilog modules