🔭 I’m currently working on RISC-V SoC Design, Verification & FPGA Prototyping

🌱 Learning SystemVerilog | UVM | ASIC Physical Design

👯 Open to collaborate on RISC-V & Custom EDA Projects

💬 Ask me about RTL, FPGA, Verilog, SystemVerilog

📫 Reach me at muddassiraliofficial@gmail.com