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Learning Chisel!!
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Learning Chisel!!

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ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communication Framework) ChipScope Server (cs_server).

Jupyter Notebook 71 11 Updated Mar 2, 2026

🔍 Zoomable Waveform viewer for the Web

JavaScript 43 2 Updated Nov 3, 2020

(System)Verilog to Chisel translator

Scala 120 11 Updated May 20, 2022

Digital Design with Chisel

TeX 915 162 Updated Apr 30, 2026

Network on Chip Implementation written in SytemVerilog

SystemVerilog 205 52 Updated Aug 27, 2022

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

Rocq Prover 167 31 Updated May 4, 2026

Converts a VCD file to a Chisel tester input file

C++ 2 2 Updated Sep 30, 2014

SoftFloat release 3

C 340 163 Updated Mar 7, 2025

Yosys Open SYnthesis Suite

C++ 4 Updated Mar 25, 2020
Verilog 81 22 Updated Feb 27, 2024

Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator

C 64 55 Updated Jun 27, 2025

Simple RISC-V 3-stage Pipeline in Chisel

Scala 609 127 Updated Aug 9, 2024

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Scala 2,258 858 Updated May 17, 2026

Hammer: Highly Agile Masks Made Effortlessly from RTL

Python 318 78 Updated Mar 6, 2026

A Library of Chisel3 Tools for Digital Signal Processing

Scala 248 40 Updated Apr 29, 2024

A coverage library for Chisel designs

Scala 11 2 Updated Mar 12, 2020

Chisel Cheatsheet

TeX 37 12 Updated Apr 13, 2023

A scala based simulator for circuits described by a LoFirrtl file

Scala 50 23 Updated Jan 12, 2023

RISC-VのCPU作った

Verilog 20 Updated Oct 21, 2019

SystemVerilog language server client for Visual Studio Code

TypeScript 23 4 Updated Dec 30, 2022

SystemVerilog linter

Rust 383 44 Updated Nov 6, 2025

SystemVerilog parser library fully compliant with IEEE 1800-2017

Rust 471 65 Updated Mar 30, 2026

SystemVerilog language server

Rust 575 32 Updated Apr 2, 2026

A tiny header-only C++ library for Sixel.

C 12 3 Updated Apr 4, 2020

Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

C 56 30 Updated Nov 24, 2019

Working Draft of the RISC-V Debug Specification Standard

Python 512 100 Updated Apr 8, 2026

RISC-V port of newlib

C 103 118 Updated Mar 15, 2022

RISCV Rust Toolchain

Makefile 119 8 Updated Jul 24, 2018
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