Stars
Control and Status Register map generator for HDL projects
ABC: System for Sequential Logic Synthesis and Formal Verification
The official GitHub mirror of the Chromium source
Python composable command line interface toolkit
A very fast and expressive template engine.
Python-based Hardware Design Processing Toolkit for Verilog HDL
An open-source HDL register code generator fast enough to run in real time.
Package manager and build abstraction tool for FPGA/ASIC development
A configurable RTL to bitstream FPGA toolchain
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Hardware implementation of the SHA-256 cryptographic hash function
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
RapidLayout: Fast Hard Block Placement of FPGA-Optimized Systolic Arrays using Evolutionary Algorithms
🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)
Verilog to Routing -- Open Source CAD Flow for FPGA Research
An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
NVIDIA Linux open GPU kernel module source
A browser automation framework and ecosystem.
A collection of Master XDC files for Digilent FPGA and Zynq boards.
Samples for CUDA Developers which demonstrates features in CUDA Toolkit
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
The ML4W OS - Dotfiles for Hyprland - An advanced and full-featured configuration for the dynamic tiling window manager Hyprland. Ready to install from a Live ISO or with the Dotfiles Installer app…