Hardware-accelerated 3×3 median filter SoC on Altera DE2 (Cyclone II) using Nios II CPU, Avalon-MM bus, and a pipelined sorting-network IP core — implemented in Verilog with Quartus II 13.0 SP1.

simple riscv

simple optimization

first commit

Automated Physical Design Flow Manager using Python.

A complete, synthesizable standard Triple DES (3DES) EDE mode encryption/decryption IP core implemented in Verilog HDL.

YOLOv5 🚀 in PyTorch > ONNX > CoreML > TFLite