Here are
26 public repositories
matching this topic...
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
Updated
Dec 15, 2025
Verilog
A collection of free educational materials, most of which are interactive or 3D animated. (See README below). You may find inspiration for measurement techniques here. They may improve your comprehension of STEM topics & even writing.
TinyTapeout submission with the SN76489 Digital Complex Sound Generator (DCSG) programmable sound generator (PSG) chip from Texas Instruments.
Updated
Nov 16, 2025
Python
Atari 2600 Open-source System-on-Chip (SoC)
Updated
Dec 10, 2025
Python
Submission template for TT02
Updated
Feb 2, 2023
Python
An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.
Updated
May 12, 2025
Scala
Logarithmic DAC for AY8913 and SN76489 programmable sound generators (Done as part of Zero To ASIC Analog course)
RISC-V ASIC design reference
TinyTapeout submission with the SAA1099 a 6-voice programmable sound generator (PSG) chip from Philips.
Updated
Nov 20, 2023
Verilog
TinyTapeout submission with the AY-3-8913 a 3-voice programmable sound generator (PSG) chip from General Instruments.
Updated
Nov 3, 2024
Python
Rule110 Cellular Automata ASIC for Tiny Tapeout 05
Updated
Nov 9, 2023
Verilog
A repository hosting the source of SoC-tapeout babysitting tutorial.
Tapeout of "Clock Domain Crossing FIFO" module using Tinytapeout(tt07) shuttle
Updated
Apr 18, 2025
SystemVerilog
ECOS Studio documentation.
Automatic Differentiation for EDA written in pure Rust with klayout (rust) verification bench
Updated
May 10, 2026
Rust
A Wavy and Rainbowy Single-Tile Submission to the TT08 Demoscene Competition
Updated
Sep 4, 2024
Verilog
A docker container with all of the tools needed for tapeout
Updated
Jun 23, 2024
Vim Script
VGA flexible video adapter for TinyQV - Crowdsourced Risc-V SoC
Updated
Sep 13, 2025
Verilog
Sovryn KAN NPU V2 SG13G2 final freeze with template-native design sources, signoff evidence, and Prometheus v16 signoff-copilot analysis.
Updated
Apr 3, 2026
Verilog
Submission for Tiny Tapeout IHP26a : High Density Serial-In Serial-Out shift register using DLHQ
Updated
Mar 23, 2026
Verilog
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