Skip to content
View MadhavDEI's full-sized avatar
0 followers · 1 following

Highlights

  • Pro

Block or report MadhavDEI

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
MadhavDEI/README.md
  • 👋 Hi, I’m @Madhav
  • 👀 I’m interested in RTL design, VLSI, Analog IC design, PCB design and much nore
  • 🌱 I’m currently learning RTL design, VLSI
  • 💞️ I’m looking to collaborate on projects of my interested fields.
  • 📫 How to reach me madhavgautam2005@gmail.com

Popular repositories Loading

  1. design_code design_code Public

  2. GCD_Calculator_Verilog GCD_Calculator_Verilog Public

    This repository includes a verilog code to implement a hardware which finds the GDC of two positive integers.

    Verilog

  3. MadhavDEI MadhavDEI Public

    Config files for my GitHub profile.

  4. ALU_VERILOG ALU_VERILOG Public

    This repository includes a verilog code to implement an ALU.

    Verilog