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1. Clock-Domain-Crossing-Synchronizers Clock-Domain-Crossing-Synchronizers Public

   Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossi…

   Verilog 64 7

2. RTL-to-GDS-Implementaton-of-Low-Power-Configurable-Multi-Clock-Digital-System- RTL-to-GDS-Implementaton-of-Low-Power-Configurable-Multi-Clock-Digital-System- Public

   It is resposable of receiving commands through UART receiver to do different system functions as register file reading/writing or doing some processing using ALU block and send result as well as CR…

   Verilog 2 1

3. Asynchronous-FIFO Asynchronous-FIFO Public

   A verilog implementation of an aynchronous FIFO (First In First Out).

   Verilog 6 1

4. 256-bit-Modular-Adder-Subtractor 256-bit-Modular-Adder-Subtractor Public

   Hardware Implementation of a Modular Adder/Subtractor

   Verilog 2

5. Memory-System-Verilog-Class-based-Testing-Environment Memory-System-Verilog-Class-based-Testing-Environment Public

   A SystemVerilog Class-Based Testing Environment to test 32*32 Memory Design

   SystemVerilog 1

6. RTL-Design-of-ARM-based-AHB-to-APB-Bridge RTL-Design-of-ARM-based-AHB-to-APB-Bridge Public

   Bridges are standard bus-to-bus interfaces that allow IPs connected to different buses to communicate with each other in a standardized way

   SystemVerilog 4 4