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1. UVM_calculator UVM_calculator Public

   This repository is meant for learning UVM using SystemVerilog. Through a verification environment, some hardware verification concepts are applied for a calculator with the four basic operations.

   SystemVerilog 8

2. UVM_Traffic_RAL UVM_Traffic_RAL Public

   This repository organizes the ChipVerify website code so that it is executable in a verification environment that uses the Register Abstraction Layer (RAL) in frontdoor and backdoor modes, as well …

   SystemVerilog 2 2

3. Switch_SV_Testbench Switch_SV_Testbench Public

   This repository organizes the ChipVerify website code so that it is executable in a verification environment that uses only the Systemverilog language resources to verify some design as an example.

   SystemVerilog

4. UVM-mult-clk-domain UVM-mult-clk-domain Public

   Forked from PedroHSCavalcante/env-mult-clk-domain

   Through a verification environment, this repository uses UVM to handle with multiple clock domains and virtual sequences.

   SystemVerilog 1 1

5. Single-Cycle_MIPS_Processor Single-Cycle_MIPS_Processor Public

   This repository holds files related to the development of a Single-Cycle Processor developed during the Digital Systems Architecture course.

   Verilog

6. AXI-DMA-Verification AXI-DMA-Verification Public

   Forked from Noman-10xe/AXI-DMA-Verification

   Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM

   VHDL