Skip to content
View MatthewNielsen27's full-sized avatar
caffeinated
caffeinated

Highlights

  • Pro

Organizations

@ecesociety

Block or report MatthewNielsen27

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Starred repositories

5 stars written in SystemVerilog
Clear filter

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog 1,765 686 Updated Feb 10, 2026

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

SystemVerilog 1,184 501 Updated May 26, 2025

RSD: RISC-V Out-of-Order Superscalar Processor

SystemVerilog 1,149 114 Updated Dec 25, 2025

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

SystemVerilog 963 329 Updated Nov 15, 2024

A directory of Western Digital’s RISC-V SweRV Cores

SystemVerilog 881 131 Updated Mar 26, 2020