PicoRV32 - A Size-Optimized RISC-V CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RTL, Cmodel, and testbench for NVDLA

SERV - The SErial RISC-V CPU

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…

3-stage RV32IMACZb* processor with debug

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

A tiny Open POWER ISA softcore written in VHDL 2008

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

An attempt to recreate the RP2040 PIO in an FPGA

CHIP-8 console on FPGA

Generic CNC firmware and driver for FPGA cards which are supported by LiteX

PACoGen: Posit Arithmetic Core Generator

Basic loadout for SQRL Acorn CLE 215/215+ board. Blinks all LEDs, outputs square waves on all 12 GPIO outputs

For use with Rudolph Lab's Project Sentry Gun