Silicon Verification Engineer | VLSI Enthusiast
- AXI Lite Cross-bar – (WIP) AXI-Lite cross-bar with 4 masters and 8 slaves.
- AXI4 Full with Burst Transfer – UVM environment supporting burst transfers and multi-ID writes.
- APB UVM – Comprehensive UVM-based verification environment for APB protocols.
- RISC-V Core – Implementation on Open FPGA Architecture.
- RISC-V_27 – SystemVerilog based 5-stage pipelined processor with hazard handling.
- MYTH – TL-Verilog based 5-stage pipelined RISC-V core.
- 16-bit Carry Look Ahead Adder – Designed using reversible logic.
- Transmission Gate Full Adder – 1-bit implementation focused on low-power logic.
- Verification: Architecting a UVM environment for AXI Crossbar.
- Memory Controllers: Architecting a DDR3 SDRAM Controller UVM environment.
- Parallel Computing: Choosing a custom project in CUDA C++.
- HDL/HVL: SystemVerilog, Verilog
- Methodologies: UVM (Universal Verification Methodology)
- Scripting & Languages: Python, Perl, C, C++
- Tools & Platforms: Linux, Open FPGA Architecture, Figma
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- Top Languages: [SystemVerilog, C++, Python, Perl]