A Python package for generating HDL wrappers and top modules for HDL sources

A Python package for creating and solving constrained randomization problems.

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

A fast usermode x86 and x86-64 emulator for Arm64 Linux

Fast PlayStation 1 emulator for x86-64/AArch32/AArch64/RV64

Public releases and CI for the Vita3K Android app

Book Reader for Android

A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.

My Python Examples

PlayStation 4 emulator for Windows, Linux and macOS written in C++

PlayStation 3 emulator and debugger

Learning FPGA, yosys, nextpnr, and RISC-V

VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation debug

Chisel Fixed-Point Arithmetic Library

SystemVerilog (.sv) to SVG visualizer using Schemdraw logic gates.

Приложение локально запускает ByeDPI и перенаправляет весь трафик через него

An AXI4 crossbar implementation in SystemVerilog

A conda-forge distribution.

SystemVerilog/Verilog support for vscode using Ctags

Really fast log explorer based on glogg project

Методичка по высшей цифровой схемотехнике + Verilog

LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled

Terminal based bit manipulator in ncurses

🤖 Just a command runner

📚 Collaborative cheatsheets for console commands

FPGA USB stack written in LiteX

Advanced and fast log explorer with support to JSON files and columns

🌀 A log file highlighter

The original high performance and small footprint system-on-chip based on Migen™