An integrated power, area, and timing modeling framework for multicore and manycore architectures

This is the top-level repository for the Accel-Sim framework.

A latex beamer template for HKUST.

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

How to Make a Computer Operating System in C++

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Ariane is a 6-stage RISC-V CPU

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

The template for VLSI project

Hammer plugins for synopsys tools

This is the FreePDK45 V1.4 Process Development Kit for the 45 nm technology

RISC-V Proxy Kernel

Free ChatGPT&DeepSeek API Key，免费ChatGPT&DeepSeek API。免费接入DeepSeek API和GPT4 API，支持 gpt | deepseek | claude | gemini | grok 等排名靠前的常用大模型。

面向开发者的 LLM 入门教程，吴恩达大模型系列课程中文版

My learning notes for ML SYS.

A graphical processor simulator and assembly editor for the RISC-V ISA

Open-source deep-learning framework for building, training, and fine-tuning deep learning models using state-of-the-art Physics-ML methods

The official repository for the gem5 computer-system architecture simulator.

Spike, a RISC-V ISA Simulator

A minimal GPU design in Verilog to learn how GPUs work from the ground up

Learning how to implement GA and NSGA-II for job shop scheduling problem in python

Lecture notes, projects and other materials for Course 'CS205 C/C++ Program Design' at Southern University of Science and Technology.

Useful CMake Examples

C++那些事

OpenXuantie - OpenC910 Core

A Style Guide for the Chisel Hardware Construction Language

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

computer vision practise