Skip to content
View Atakumi's full-sized avatar
0 followers · 3 following

Block or report Atakumi

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Stars

1 star written in Verilog
Clear filter

bendyer / adat-verilog

Altera Cyclone FPGA cores for dealing with ADAT I/O, written in Verilog.

Verilog 20 1 Updated Mar 17, 2010