Advanced CLI tool for automating Machine Learning (AutoML) using state-of-the-art deep learning models to apply transfer learning with multiple tuning methods and architecture modifications to pret…

Research about dataflow architecture

The sigmiod and tanh functions in GRU are inspired by "A CORDIC-Based Architecture with Adjustable Precision and Flexible Scalability to Implement Sigmoid and Tanh Functions, IEEE International Sym…

VeeR EH1 core

A minimal GPU design in Verilog to learn how GPUs work from the ground up

GPGPU microprocessor architecture

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*

bootOS is a monolithic operating system in 512 bytes of x86 machine code.

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

An MLIR-based toolchain for AMD AI Engine-enabled devices.

ASIC design toolkit with templates and opensource pdks

FPGA design toolkit with templates and standard modules

A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1

CircuitPython - a Python implementation for teaching coding with microcontrollers

RT-Thread is an open source IoT Real-Time Operating System (RTOS). https://rt-thread.github.io/rt-thread/

MicroPython - a lean and efficient Python implementation for microcontrollers and constrained systems

You like pytorch? You like micrograd? You love tinygrad! ❤️

Minimalist 32-bit RISC-V core with C & Rust apps.

A basic working RISCV emulator written in C

Xv6 for RISC-V

Opensource DDR3 Controller

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).

Writing an OS in 1,000 lines.

Envision a future where every student can read all the code of a teaching operating system.

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end produ…