RTL logic synthesis

A configurable RTL to bitstream FPGA toolchain

RAD-Gen is a tool for silicon area/timing/power implementation results of hard (ASIC) components, FPGA fabric circuitry, and circuit modeling of 3D devices/packaging

Some useful scripts to run vpr or parse the results

A Python subset for a better MLIR programming experience

Verilog to Routing -- Open Source CAD Flow for FPGA Research

hyperloop go zoom

The core software that operates our pod #1. This includes controls, communications, testing suites, control panel, etc.

A SYCL-specific LLVM-to-MLIR converter