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@tokenbender
tokenbender tokenbender
Sparse and Efficient Language Modelling

Sparse and Efficient Language Modelling

@Ravenwater
Theodore Omtzigt Ravenwater
Computer Architect and custom compute engine developer for robotics, computer vision, and high-performance computing applications.

Stillwater Supercomputing, Inc. Freeport, Maine

@jun1okamura
Jun OKAMURA jun1okamura
IEEE Senior member

AIST Solutions / Trigence Semiconductor Tokyo

@dwjgt
Dongwon Jang dwjgt

Georgia Institute of Technology Atlanta, GA

@ChenHaoHSU
Chen-Hao Hsu ChenHaoHSU

The University of Texas at Austin Austin, TX, USA

@Brilight
王启盼 (Wang Qipan) Brilight
PhD student at Peking University, majoring in EDA, and AI Chips

Peking University Beijing

@KrzysztofHerman
Krzysztof Herman KrzysztofHerman
IHP Open PDK Developer

IHP GmbH

@gabrielmaranhao
Gabriel Maranhão Soares gabrielmaranhao
Graduated in Computer Engineering. PhD degree at Federal University of Santa Catarina, with emphasis in Microletronics, Analog Circuits, PDK, Compact Modeling.

imec Leuven - Belgium

@hpretl
Harald Pretl hpretl
Professor @ JKU, analog/mixed-signal/RF integrated circuits

Johannes Kepler University Linz, Austria

@mithro
Tim 'mithro' Ansell mithro
Founder and Leader of @timvideos

@wafer-space Adelaide, Australia

@FabriceSalvaire
Fabrice Salvaire FabriceSalvaire
Scientific Software Architect

Paris France

@KCL-Planning
Planning at King's College London KCL-Planning
Planning Research at King's is focused around domain-independent planning.

King's College London

@yarox
Adrian Martin yarox

The Wonder Lab Paradise

@haz
Christian Muise haz

Queen's University Kingston, Ontario, Canada

@uhbif19
Gregory Gerasev uhbif19
Python and Haskell programmer. Quality code enthusiast.

@investengine Tbilisi

@andreasabel
Andreas Abel andreasabel

Chalmers and Gothenburg University Gothenburg, Sweden

@PDTypes
PDTypes PDTypes
Code supporting Planning Languages and Types work done at Heriot-Watt and St Andrews Universities
@asyncvlsi
Yale Asynchronous VLSI and Architecture Group asyncvlsi
Research group led by Rajit Manohar working on asynchronous digital circuits and systems
@mkkassem
Mohamed Kassem mkkassem

efabless.com The Universe

@freecores
FreeCores freecores
A home for open source hardware cores
@EarthICTSPC
Earth ICT, SPC EarthICTSPC
"Earth Health Monitor" (tm)

United States of America

@RTimothyEdwards
R. Timothy Edwards RTimothyEdwards

Open Circuit Design Poolesville, Maryland

@hishamelreedy
Hisham Elreedy hishamelreedy
"وقل ربى زدنى علما"

Cairo University, Faculty of Engineering

@zeeshanrafique23
Zeeshan Rafique zeeshanrafique23
Hardware Engineer | RISC-V Ambassador

@semidynamics Barcelona, Spain

@vikraman
Vikraman Choudhury vikraman
Chancellor's Fellow

University of Strathclyde Glasgow, UK

@conal
Conal Elliott conal
Play/learn/work with me: https://github.com/conal/Collaboration

(open to employment) San Andreas, California, USA

@kunalg123
Kunal Ghosh kunalg123
Kunal Ghosh Co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd.

VLSI System Design Corp. Pvt. Ltd. Bangalore, India

@mguthaus
Matt Guthaus mguthaus

UCSC Santa Cruz, CA

@manish-kj
Manish Kumar Jaiswal manish-kj

The University of Hong Kong Hong Kong

@piranna
Jesús Leganés-Combarro piranna
Über-geek, lead developer @NodeOS, WebRTC guru, free software advocate. I <3 science and technology :-) Previously @Kurento, @dyte-in, CTO @UnifyMe & @lingbe

@Mafalda-SFU Madrid, Spain - Abu Dhabi, UAE