module beautlin_s (
input logic clk,
input logic curiosity,
output logic innovation
);
localparam string ROLE = "Apprentice @ C-DAC Bangalore";
localparam string FOCUS = "Crypto IP Design & Simulation";
localparam string INTEREST = "RTL Design | Computer Architecture | AI Accelerators";
localparam string HDL = "SystemVerilog | UVM";
localparam string TOOLS = "Cadence Xcelium | Jasper | Linux";
localparam string PROTOS = "AXI4 | AHB | UART | SPI";
// The question that drives me:
// How do we build hardware that runs ML workloads faster and smarter?
// → RISC-V | Accelerator Architectures | Hardware-Software Co-design
always_ff @(posedge clk)
if (curiosity) innovation <= 1'b1;
endmodule| Where | Role | What |
|---|---|---|
| C-DAC Bangalore | Apprentice (Sept 2025 – Present) | Crypto IP Design & Simulation |
| IIT Madras – RISE Lab | Research Intern (Jan – Apr 2025) | ML benchmarking on the Shakti RISC-V processor |
| IISc – DREAM Lab | Research Intern (Nov 2023 – Jan 2024) | Time & power prediction for DNN workloads on edge accelerators |
| IIITDM – HPRCSE Lab | Research Intern (May – Jun 2023) | Fault mitigation for mission-critical control circuits |
PowerTrain: Fast, Generalizable Time and Power Prediction Models for DNN Workloads on Accelerated Edges Accepted at FGCS'24 · IISc DREAM Lab
Profiled DNN inference on NVIDIA Jetson Xavier & Orin. Built generalizable models for power and latency — the kind of hardware-software boundary work that matters when designing accelerators.
Evolvable Hardware for Fault Mitigation in Control Circuits Poster at VLSID'24 · IIITDM
Modelled a Satellite FSM in Verilog, implemented on FPGA to demonstrate evolvable hardware for fault tolerance in mission-critical systems.
RTL & Verification
EDA Tools
Protocols
Programming & ML (supporting)
SM4 Cryptographic IP Core (C-DAC, Dec 2025)
Full SM4 block cipher in SystemVerilog — key schedule, 32-round datapath, CBC/CFB cipher modes via control FSM, AXI4-compliant wrapper. Verified with self-checking testbench on Cadence Xcelium.
RISC-V 5-Stage Pipelined Processor (edX – MYP30H, May 2023)
Designed a complete 5-stage in-order pipeline in TL-Verilog with hazard detection and data forwarding. Simulated on Makerchip.
"First, solve the problem. Then, write the code."