Stars
[ICML'21 Oral] I-BERT: Integer-only BERT Quantization
A model library for exploring state-of-the-art deep learning topologies and techniques for optimizing Natural Language Processing neural networks
Pre-trained Deep Learning models and demos (high quality and extremely fast)
Transformer related optimization, including BERT, GPT
🤗 Transformers: the model-definition framework for state-of-the-art machine learning models in text, vision, audio, and multimodal models, for both inference and training.
Accepted by New Trends in Image Restoration and Enhancement workshop (NTIRE), in conjunction with CVPR 2024.
Verilog implementation of the generator of DCGAN on FPGA
A Verilog design of LeNet-5, a Convolutional Neural Network architecture
This is a 4*5 PE array for LeNet accelerator based on FPGA.
【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器
some interesting demos for starters
FPGA accelerated TinyYOLO v2 object detection neural network
Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
A Pytorch implementation of MoveNet from Google. Include training code and pre-trained model.
Generator of verilog description for FPGA MobileNet implementation
A PyTorch implementation of MobileNet V2 architecture and pretrained model.
Tile based architecture designed for computing efficiency, scalability and generality
Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
Website for the OpenROAD tutorial held at the MICRO 2022 conference
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/