This repository repository is part of the AIST TSN project. It includes Ethernet Frame Crafter & Capture (EFCC), a flexible FPGA-based frame generation and capture measurement tool for TSN research and development. EFCC is capable of generating multiple TSN flows with different characteristics, where the frame size, frame rate, and burst size are independently set for each flow. In addition, it can record the arrival times of all the frames with a high-precision hardware clock without any loss of the arrival time records, even with the shortest frame size. It supports GbE and 10GbE. IP and designs for an AMD Xilinx KC705 FPGA evaluation board and Alveo U250/U45N accelerator cards are included:

• Ethernet Frame Crafter
  • This module generates and transmits Ethernet frames based on the information written in BRAM.
  • Specification
• Ethernet Frame Capture
  • This module outputs the input Ethernet frames as they are with zero latency.
  • It also extracts the ID information from the frames received from the Ethernet Frame Crafter and records the ID information and the time when the frames were input to BRAM.
  • Specification
• Sample design for 1GbE (KC705)
  • FPGA design docs
• Sample design for 10GbE (U45N and U250)
  • FPGA design docs

When using the provided designs in this repository, please refer to the following citation:

Akram BEN AHMED, Takahiro HIROFUCHI and Takaaki FUKAI, "EFCC: Ethernet Frame Crafter & Capture for TSN Research", The 50th IEEE Conference on Local Computer Networks (LCN2025), pp. 1-9, October 2025, doi: 10.1109/LCN65610.2025.11146312, https://ieeexplore.ieee.org/document/11146312

Paper ; Slides

Best Paper Award Candidate🏆

A license for AMD Tri-mode Ethernet MAC (TEMAC) IP is required to synthesize the KC705 design. You can obtain the evaluation license free of charge.

Please prepare the following environment.

• Ubuntu 20.04.3 LTS
• CMake 3.14 or later
• Vivado v2022.1
  • Set Vivado to PATH
• Set XILINXD_LICENSE_FILE to environment variables

Change the PATH search order to avoid using the old cmake included in the Vivado directory.

(after vivado setting. e.g. "source <VIVADO_ROOT>/settings64.sh")
export PATH=/usr/local/bin:/usr/bin:$PATH

All designs will be built by running the command below.

cd <Repository top>
./build_device.sh impl_all

Alternatively, build them individually by doing the following.

cd <Repository top>
./build_device.sh impl_sample_design-1g
./build_device.sh impl_sample_design-10g_u45n
./build_device.sh impl_sample_design-10g_u250

Bitstreams will be generated below.

• Sample design
  • build-device/vivado/sample_design-1g/sample_design-1g.prj/sample_design-1g.runs/impl_1/design_1_wrapper.bit
  • build-device/vivado/sample_design-10g/sample_design-10g_u45n.prj/sample_design-10g_u45n.runs/impl_1/design_1_wrapper.bit
  • build-device/vivado/sample_design-10g/sample_design-10g_u250.prj/sample_design-10g_u250.runs/impl_1/design_1_wrapper.bit

Note: If you prefer to use a GUI, launch Vivado and program the board using the Hardware Manager. The following instructions explain the command-line procedure using xsdb.

1. Set PYTHONPATH

export PYTHONPATH=$(pwd)/../aist-tsn-switch/util/python

2. Get a list of devices with their unique IDs, and note the number displayed to the left of your target device. If multiple identical devices are connected, distinguish them using the unique JTAG ID shown at the end within the parentheses.

• KC705: xc7k325t
• U45N: xcu26_ux35
• U250: xcu250

python3 ../aist-tsn-switch/util/common/describe_xsdb_target.py
xsdb server launched.
1: xc7k325t (Digilent JTAG-SMT1 210203AB909BA)
    2: Legacy Debug Hub (Digilent JTAG-SMT1 210203AB909BA)
        3: JTAG2AXI (Digilent JTAG-SMT1 210203AB909BA)
4: APU (Digilent Zed 210248687025)
    5: ARM Cortex-A9 MPCore #0 (Digilent Zed 210248687025)
    6: ARM Cortex-A9 MPCore #1 (Digilent Zed 210248687025)
7: xc7z020 (Digilent Zed 210248687025)
    8: Legacy Debug Hub (Digilent Zed 210248687025)
        9: JTAG2AXI (Digilent Zed 210248687025)
10: xcu26_ux35 (Xilinx Alveo-ADK-2-0 FT4232H 507711333S04AA)
    11: Legacy Debug Hub (Xilinx Alveo-ADK-2-0 FT4232H 507711333S04AA)

3. Start xsdb.

(after vivado setting. e.g. "source <VIVADO_ROOT>/settings64.sh")
xsdb

4. Connect to the hw_server.

xsdb% conn

5. List the available JTAG targets.

xsdb% target
  1  xc7k325t
     2  Legacy Debug Hub
        3  JTAG2AXI
  4  APU
     5  ARM Cortex-A9 MPCore #0 (Running)
     6  ARM Cortex-A9 MPCore #1 (Running)
  7  xc7z020
     8  Legacy Debug Hub
        9  JTAG2AXI
 10  xcu26_ux35
    11  Legacy Debug Hub

6. Specify the number you noted in step 2.

# Example: Selecting the KC705 from the target list above
xsdb% target 1

7. Program the bitstream by specifying its path.

xsdb% fpga <bitstream_path>

├── 3rdparty    : 3rd-party projects
├── cmake       : Common CMake files
├── device      : Source code for device including FPGA
├── docs        : Documentation
├── evaluation  : Evaluation data
├── example     : Examples written in Jupyter Notebook for 1G sample design
├── example_10g : Examples written in Jupyter Notebook for 10G sample design
└── util        : Helper scripts for TSN EFCC

• .gitignore: Git ignore
• .gitmodules: Git submodule
• build_device.sh: Build device script
• README.md: This file

Copyright (c) 2024-2026 National Institute of Advanced Industrial Science and Technology (AIST) All rights reserved.

This software is released under the MIT License.

• Upcoming
  • Added FPGA design of 10GbE EFCC for U45N and U250
  • Design documentation for 10GbE EFCC
  • Jupyter Notebook tutorials for 10GbE EFCC
• v1.0 (Aug 2025)
  • Initial release
  • FPGA design of 1GbE EFCC for KC705
  • Design documentation for 1GbE EFCC
  • Jupyter Notebook tutorials for 1GbE EFCC
  • Evaluation scripts and results for our LCN paper
  • Utility scripts

The Continuum Computing Architecture Research Group (CCARG), Intelligent Platforms Research Institute (IPRI), the National Institute of Advanced Industrial Science and Technology (AIST), Japan.

Research Group Leader: Takahiro Hirofuchi, Ph.D.

This program is based on results obtained from the project, "Research and Development Project of the Enhanced infrastructures for Post 5G Information and Communication Systems" (JPNP20017), commissioned by the New Energy and Industrial Technology Development Organization (NEDO).