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RISCV_SingleCycle Public
RISC V single cycle processor design and implementation using Bluespec System Verilog
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tt10-verilog-vlsi Public template
Forked from TinyTapeout/tt10-verilog-templateSubmission template for Tiny Tapeout 10 - Verilog HDL Projects
Verilog Apache License 2.0 UpdatedApr 8, 2025 -
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Plant-Disease-Detector Public
Forked from root458/Plant-Disease-DetectorA Flutter app that detects a plant's disease given a photo of an affected part of the plant.
Dart UpdatedNov 16, 2024 -
MATLAB-based Digital Signal Processing Laboratory with examples of convolution, DFT, FIR filtering, and more. Each folder includes code and individual README files for theoretical explanations.
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tt06-verilog-template-tkmce Public template
Forked from TinyTapeout/tt06-verilog-templateSubmission template for Tiny Tapeout 6 - Verilog HDL Projects
Tcl Apache License 2.0 UpdatedMay 3, 2024 -
verilog-uart Public
Forked from hell03end/verilog-uartSimple 8-bit UART realization on Verilog HDL.
Verilog MIT License UpdatedApr 27, 2024 -
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ASIC-Implementation-UART Public
Forked from abdelazeem201/ASIC-Implementation-UARTVerilog MIT License UpdatedMar 30, 2022
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