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  • Shanghai Jiao Tong University
  • Shanghai
  • 09:53 (UTC +08:00)

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1 star written in VHDL
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j3soon / Handwritten-Digit-Recognition-Painter

A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.

VHDL 24 5 Updated Oct 29, 2023