ECE Undergraduate @ NIT Warangal
Low-level thinker. Hardware-first mindset. Architecture obsessed
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🧩 Engineering sophomore obsessed with how things actually work
🔩 I operate close to silicon and system level, timing paths and architectural bottlenecks
- Branch prediction internals
- Cache behavior and replacement logic
- Pipeline-level reasoning
- Performance vs hardware cost tradeoffs
- ML models constrained by latency and area
- Online learning on real hardware
- Accuracy is useless without feasibility
- RTL design (Verilog)
- Timing-aware design decisions
- Sensor → hardware → inference pipelines
- Prototyping ideas that don’t hide behind simulators
🟦 Computer Architecture
🟦 Verilog
🟦 FPGA Architecture
🟦 Timing & Resource Analysis
🟨 C / C++
🟨 Python (modeling & validation)
🟨 MATLAB
🟨 Linux
🟨 Git
⚡ Deepening architecture-level ML understanding
⚡ Translating research ideas into RTL
⚡ Long-term: systems research
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